Results 241 to 250 of about 4,405,974 (289)

Capacitor-less 1-transistor DRAM

IEEE International SOI Conference SOI-02, 2002
We review the current status of the 1T-DRAM development, illustrate how this concept can be extended to fully depleted (FD) SOI, and demonstrate a first circuit application. A memory circuit area reduction of 3 to 10 times can be achieved when compared to DRAM or SRAM reference circuits respectively.
Fazan, P., Okhonin, S., Nagoga, M., Sallese, Jean-Michel, Portmann, L., Ferrant, R., Kayal, M., Pastre, M., Blagojevic, M., Borschberg, A., Declercq, M.   +10 more
openaire   +2 more sources

A new capacitor-less LED drive

2016 13th International Multi-Conference on Systems, Signals & Devices (SSD), 2016
In this paper a new capacitor-less LED drive is proposed. The design is based on the utilization of the internal capacitance of the LED to replace the smoothing capacitor. LED lighting systems usually have many LEDs for better illumination that can reach multiple tens of LEDs. Such configuration can be utilized to enlarge the total internal capacitance
Munir Ahmad Al-Absi, Zainulabideen J. Khalifa, Alaa E. Hussein   +2 more
openaire   +1 more source

Capacitor-Less Memristive Integrate-and-Fire Neuron with Stochastic Behavior

2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2021
Stochasticity in networks of artificial spiking neurons has been theorized to unlock some of the adaptive learning capabilities of biology. To realize this behavior, systems must be designed to operate probabilistically, looking for patterns in a distribution rather than performing a deterministic mathematical function. In order to design these systems
Samuel D. Brown, Md Musabbir Adnan, Mst Shamim Ara Shawkat, Garrett S. Rose   +3 more
openaire   +1 more source

A capacitor-less 1T-DRAM cell

IEEE Electron Device Letters, 2002
A simple true 1 transistor dynamic random access memory (DRAM) cell concept is proposed for the first time, using the body charging of partially-depleted SOI devices to store the logic "1" or "0" binary states. This cell is two times smaller in area than the conventional 8F/sup 2/ 1T/1C DRAM cell and the process of its manufacturing does not require ...
S. Okhonin, M. Nagoga, J.M. Sallese, P. Fazan   +3 more
openaire   +1 more source

A Capacitor-Less CMOS Neuron Circuit for Neuromemristive Networks

2019 17th IEEE International New Circuits and Systems Conference (NEWCAS), 2019
CMOS neuron circuits used to implement neuromorphic chips require extensive circuitry to program the memristive cell, thus eliminating most of the density advantage gained by the adoption of memristive synapses. This paper presents a CMOS neuron circuit that provides a compact and cost-efficient programming interface in which semiconductor capacitors ...
Hassen Aziza, Mathieu Moreau, Annie Pérez, Arnaud Virazel, Patrick Girard 0001   +4 more
openaire   +1 more source

Output-Capacitor-Less LDO with High PSR

2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), 2019
A low-dropout regulator (LDO) with high power supply ripple rejection (PSR) and capacitor-free is presented in this paper. The LDO proposes a PSR enhancement module based on the analysis of the power supply noise transmission path. It uses the Q-reduction circuit to reduce the required on-chip capacitor and the load on the minimum required output.
Yue Zhang, Ningmei Yu, Zhiqiang Jiang, Yuanyuan Wu   +3 more
openaire   +1 more source

A-RAM: Novel capacitor-less DRAM memory

2009 IEEE International SOI Conference, 2009
A totally different capacitor-less, single-transistor memory cell (1T-DRAM) is proposed and documented. Its novelty comes from the body partitioning in two distinct regions, where electrons and holes are respectively confined. As compared to earlier 1T-DRAMs, the coexistence and coupling of electrons and holes is maintained even in ultrathin fully ...
Noel Rodriguez, Sorin Cristoloveanu, Francisco Gamiz   +2 more
openaire   +1 more source

Real DC capacitor-less active capacitors

2017 IEEE Applied Power Electronics Conference and Exposition (APEC), 2017
Single-phase pulse width modulation H-bridge active capacitors have second-order harmonic ripple voltages on the DC bus. The second-order harmonic power is usually filtered by a bulk capacitor on the DC bus to maintain a constant dc-bus voltage, which results in low power density. However, in applications like active capacitors, a larger DC bus voltage
Yunting Liu, Fang Zheng Peng
openaire   +1 more source

A SOI capacitor-less 1T-DRAM concept

2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207), 2002
A simple 1T DRAM cell concept is proposed for the first time. It exploits the body charging of PD SOI devices to store the information. This cell is at least two times smaller in area than the conventional 1T/1C DRAM cell and does not require the integration of a storage capacitor.
S. Okhonin, M. Nagoga, J.M. Sallese, P. Fazan   +3 more
openaire   +1 more source

Capacitor-less memory: Advances and challenges

2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2016
Several types of floating-body capacitorless 1TD-RAM memory cells are reviewed and compared. We focus on the recently proposed concepts (MSDRAM, A2RAM and Z2FET), by addressing the device architecture and fabrication, operating mechanisms, and scaling issues.
openaire   +1 more source