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CMOS IMAGE SENSORS WITH COMPRESSIVE SENSING ACQUISITION
, 2013 Mohammadreza Dadkhah
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CMOS clamped-swing logic (CMOS CSL) and CMOS differential clamped-swing logic (CMOS DCSL)
[1992] Proceedings of the 35th Midwest Symposium on Circuits and Systems, 2003Two new static CMOS logic circuits called the CMOS clamped-swing logic and the CMOS differential clamped-swing logic are proposed and analyzed. In these two new logic circuits, the internal circuit used to realize the logic functions has a small voltage swing, whereas the output signal has a normal swing compatible with other CMOS logic. Both new logic
H.-Y. Huang, C.-Y. Wu
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Mitigating defective CMOS to Non-CMOS vias in CMOS/Molecular memories
10th IEEE International Conference on Nanotechnology, 2010CMOS/Molecular (CMOL) memory is one of the emerging memory technologies that promises increased data storage, reduced power consumption and minimized fabrication complexity. The fabrication of these memories is based on the stacking of non-CMOS-based memory cell array on the top of CMOS-based peripheral circuits.
Nor Zaidi Haron, Said Hamdioui
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Nanoelectronics devices: More CMOS, fusion CMOS and beyond CMOS
2009 IEEE Asian Solid-State Circuits Conference, 2009We are facing several difficulties with shrinking LSI chips, such as leakage currents/power consumption, variability, huge costs in R&D and production. Major semiconductor market will be absolutely dependent on further shrinking of Si CMOS transistors with improving transistor structures and lowering drive voltage, increasing wafer diameter and 3D ...
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ST-CMOS (Stacked Transistors CMOS): A double-poly-NMOS-compatible CMOS technology
1981 International Electron Devices Meeting, 1981A modified double-poly NMOS technology is proposed, providing CMOS structures. The P-channel transistors are made in the second poly layer. The process scheme is standard, except for the laser annealing step. A method of laser annealing of processed [even non-planar] samples is derived, giving rise to a concept of selective annealing.
J.P. Colinge, E. Demoulin
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Graphene for CMOS and Beyond CMOS Applications
Proceedings of the IEEE, 2010Owing in part to complementary metal-oxide-semiconductor (CMOS) scaling issues, the semiconductor industry is placing an increased emphasis on emerging materials and devices that may provide a solution beyond the 22-nm node. Single and few layers of carbon sheets (graphene) have been fabricated by a variety of techniques including mechanical ...
Sanjay K. Banerjee +6 more
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Adiabatic-CMOS/CMOS-adiabatic logic interface circuit
International Journal of Electronics, 2000This paper describes the design of an adiabatic-CMOS/CMOS-adiabatic logic interface circuit for a group of low-power adiabatic logic families with a similar clocking scheme. The circuit provides interfacing between several recently proposed low-power adiabatic logic circuits and traditional digital CMOS circuits. One advantage of this design is that it
K. T. Lau, W. Y. Wang, K. W. Ng
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Pulsed power supply CMOS-PPS CMOS
Proceedings of 1994 IEEE Symposium on Low Power Electronics, 2002Low power dissipation using conventional CMOS circuits can be achieved if the power supply lead is ramped repetitively between VDD and VSS. During the power-down edge, the state of the chip is stored on parasitic capacitances. This quasi-static CMOS circuit technique is called PPS (Pulsed Power Supply) CMOS and reduces the power dissipation over ...
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