Results 341 to 350 of about 627,439 (398)

Mitigating defective CMOS to Non-CMOS vias in CMOS/Molecular memories

10th IEEE International Conference on Nanotechnology, 2010
CMOS/Molecular (CMOL) memory is one of the emerging memory technologies that promises increased data storage, reduced power consumption and minimized fabrication complexity. The fabrication of these memories is based on the stacking of non-CMOS-based memory cell array on the top of CMOS-based peripheral circuits.
Nor Zaidi Haron, Said Hamdioui
openaire   +2 more sources

CMOS clamped-swing logic (CMOS CSL) and CMOS differential clamped-swing logic (CMOS DCSL)

[1992] Proceedings of the 35th Midwest Symposium on Circuits and Systems, 2003
Two new static CMOS logic circuits called the CMOS clamped-swing logic and the CMOS differential clamped-swing logic are proposed and analyzed. In these two new logic circuits, the internal circuit used to realize the logic functions has a small voltage swing, whereas the output signal has a normal swing compatible with other CMOS logic. Both new logic
Han-Hsiang Huang, Chung-Yu Wu
openaire   +2 more sources

Alternative CMOS or alternative to CMOS?

Microelectronics Reliability, 2001
Abstract We point out the main issues to address in order to investigate and push the limits of CMOS technology. The demand for low voltage, low power and high performance are the great challenges for engineering of sub-0.10 μm gate length devices. The possible solutions are reviewed through the issues in gate/channel and substrate, source and drain ...
openaire   +2 more sources

RF CMOS RELIABILITY

International Journal of High Speed Electronics and Systems, 2001
In this chapter the effects of hot carrier on the reliability of NMOS transistors are investigated. First, it is explained why the hot carrier issue can be important in RF CMOS circuits. Important mechanisms of hot carrier generation are reviewed and some of the techniques used in the measurement of hot carrier damages are explained.
Sasan Naseh, M. Jamal Deen
openaire   +2 more sources

CMOS is dead … long live CMOS!

2007 IEEE Hot Chips 19 Symposium (HCS), 2007
This article consists of a collection of slides from the author's conference presentation on the future of CMOS technologies. Some of the specific topics discussed include: the market for CMOS scaling; design considerations for materials plus CMOS scaling; the future that considers devices plus materials plus CMOS scaling; and new areas of future chip ...
openaire   +2 more sources

Implementation of CMOS oscillator for CMOS SAW resonator

2016 Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP), 2016
This work presents a design and measurement of pierce oscillator circuit for microelectromechanical system (MEMS) SAW resonator. The pierce oscillator circuit was fabricated using MIMOS 0.35um CMOS technology process. The pierce oscillator circuit provides gain to offset the losses of the resonator.
Jamilah Karim, S Anis Nurashikin Nordin
openaire   +2 more sources

Nanoelectronics devices: More CMOS, fusion CMOS and beyond CMOS

2009 IEEE Asian Solid-State Circuits Conference, 2009
We are facing several difficulties with shrinking LSI chips, such as leakage currents/power consumption, variability, huge costs in R&D and production. Major semiconductor market will be absolutely dependent on further shrinking of Si CMOS transistors with improving transistor structures and lowering drive voltage, increasing wafer diameter and 3D ...
openaire   +2 more sources

Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas

IEEE J. Solid State Circuits, 1990
An alpha -power-law MOS model that includes the carrier velocity saturation effect, which becomes prominent in short-channel MOSFETs, is introduced. The model is an extension of Shockley's square-law MOS model in the saturation region. Since the model is
Ieee TAKAYASU SAKURAI MEMBER, Ieee A. RICHARD NEWTON FELLOW   +1 more
semanticscholar   +1 more source

ST-CMOS (Stacked Transistors CMOS): A double-poly-NMOS-compatible CMOS technology [PDF]

1981 International Electron Devices Meeting, 1981
A modified double-poly NMOS technology is proposed, providing CMOS structures. The P-channel transistors are made in the second poly layer. The process scheme is standard, except for the laser annealing step. A method of laser annealing of processed [even non-planar] samples is derived, giving rise to a concept of selective annealing.
Jean-Pierre Colinge, E. Demoulin
openaire   +1 more source

Pulsed power supply CMOS-PPS CMOS

Proceedings of 1994 IEEE Symposium on Low Power Electronics, 2002
Low power dissipation using conventional CMOS circuits can be achieved if the power supply lead is ramped repetitively between VDD and VSS. During the power-down edge, the state of the chip is stored on parasitic capacitances. This quasi-static CMOS circuit technique is called PPS (Pulsed Power Supply) CMOS and reduces the power dissipation over ...
openaire   +2 more sources