Results 181 to 190 of about 53,559 (283)

Design and simulation of a p-type dual interbridge treeFET with comprehensive DC, analog/RF, and linearity analysis for CMOS circuit applications. [PDF]

Sci Rep
Mounika S, Nanda U.
europepmc   +1 more source

Harnessing ferroptosis from multilayer defense networks to nanoplatforms for specific cancer therapy

BMEMat, EarlyView.
Nanomaterials target metabolically‐regulated ferroptosis for cancer therapy. Iron‐based or alternative nanoplatforms integrate ferroptosis with chemotherapy, immunotherapy, or radiotherapy. They enable stimulus‐responsive therapies (photothermal, photodynamic, sonodynamic) activated by near‐infrared, light, or ultrasound, achieving potent synergistic ...
Xinyue Xu, Xuejian Wang, Wenyan Jiang, Wan Hairul Anuar Kamaruddin, Chunyan Fang, Pengfei Zhang   +5 more
wiley   +1 more source

A review of SPAD array chip design for direct time-of-flight LiDAR. [PDF]

Discov Nano
Mo L, Huang S, Yang Y, Ren TL.
europepmc   +1 more source

Perovskite Photodetectors at the Intelligence Frontier: From Tunable Materials to Adaptive Optoelectronic Systems

Carbon Energy, EarlyView.
This comprehensive review presents a progressive roadmap for perovskite vision detectors. Centered on perovskite‐based artificial perception, the graphic illustrates a systematic evolution: starting with fundamental material engineering and device architectures, advancing toward complex functional strategies such as flexible neuromorphic imaging ...
Chenglong Li, Wei Qu, Deepak Kumar, Naini Jain, Nur Wardina Syahirah binti Mohamad Fadil, Nur Najiha binti Ahmad Rasid, Emannuel Kymakis, Maria Vasilopoulou, Chunxiong Bao, Feng Gao, Peng Gao, Sanjeev Kumar Sharma, Mohammad Khaja Nazeeruddin, Abd. Rashid bin Mohd Yusoff, Haotong Wei   +14 more
wiley   +1 more source

A K-Band Four-Channel Beamformer with Temperature Compensation Based on 65 nm CMOS Process. [PDF]

Micromachines (Basel)
Wang C, Liu Y, Liao X, Zhang F, Deng C, Liu Y, Sun W, Guan H, Zhou D.   +8 more
europepmc   +1 more source

On the Design of a Class of Analog Filters Whose Impulse Response Is a Mittag‐Leffler Function

International Journal of Circuit Theory and Applications, EarlyView.
Fractional‐order filters whose impulse response is a Mittag‐Leffler (M‐L) function in any of its known forms are summarized in this work. Simulation results using Cadence and experimental results using an FPAA validate the introduced concept. ABSTRACT Fractional‐order filters whose impulse response is a Mittag‐Leffler (M‐L) function in any of its known
Julia Nako, Costas Psychalinos, Ahmed S. Elwakil, Brent J. Maundy   +3 more
wiley   +1 more source

A neuromorphic processor with on-chip learning for beyond-CMOS device integration. [PDF]

Nat Commun
Greatorex H, Richter O, Mastella M, Cotteret M, Klein P, Fabre M, Rubino A, Soares Girão W, Chen J, Ziegler M, Bégon-Lours L, Indiveri G, Chicca E.   +12 more
europepmc   +1 more source

A 40.68‐MHz Active Rectifier Using PLL and PWM Control of DC‐DC Converter for ON/OFF Delay Compensation

International Journal of Circuit Theory and Applications, EarlyView.
A ramp‐based phase‐locked loop (RPLL) active rectifier operating at 40.68 MHz compensates switching delay variations to improve phase alignment. The proposed architecture achieves 90.3% peak power conversion efficiency and 98.0% voltage conversion ratio for high‐frequency wireless power transfer in implantable medical devices.
Woorim Lee, Sungmin Shin, Seongbin Kwon, Geonwoo Baek, Jongyeop Kim, Franklin Bien   +5 more
wiley   +1 more source

Metrics for spin-based computing. [PDF]

Nat Rev Phys
Kurebayashi H, Finocchio G, Everschor-Sitte K, Gartside JC, Taniguchi T, Litvinenko A, Kumar A, Åkerman J, Vasilaki E, Selçuk K, Çamsarı KY, Madhavan A, Fukami S.   +12 more
europepmc   +1 more source

Subthreshold Time‐Mode All‐Digital DLL With Built‐In Linearization

International Journal of Circuit Theory and Applications, EarlyView.
This paper presents a subthreshold time‐mode all‐digital delay‐locked loop (DLL) for low‐frequency clock generation. The large and tunable delay of the DLL is obtained using a static inverter delay line whose supply voltage is in the vicinity of 100 mV and adjustable by varying supply voltage. Phase error is processed by a time‐mode proportional block (
Fei Yuan, Wenhao Wu, Yushi Zhou
wiley   +1 more source