Results 221 to 230 of about 769 (247)

Perovskite Microwires for Room Temperature Exciton-Polariton Neural Network. [PDF]

Adv Mater
Opala A, Tyszka K, Kędziora M, Furman M, Rahmani A, Świerczewski S, Ekielski M, Szerling A, Matuszewski M, Piętka B.   +9 more
europepmc   +1 more source

A cochlea bio-inspired tunable piezoelectric cantilever array MEMS microphone: comprehensive study. [PDF]

Microsyst Nanoeng
Zheng Z, Ke Q, Luo H, Zhang P, Yan Z, Wang C, Kraft M, Martins RP, Mak PI, Wang Y.   +9 more
europepmc   +1 more source

Phase-Changing Vanadium Oxides for Electromagnetic Radiation Management. [PDF]

Small Sci
Taha M, Daeneke T, Walia S.
europepmc   +1 more source

Robust design of low power CMOS analogue integrated circuits

IEE Proceedings - Circuits, Devices and Systems, 2001
As feature sizes move into the deep submicron ranges and power supply voltages are reduced, the effect of both device mismatch and inter-die process variations on the performance and reliability of analogue integrated circuits is magnified. The statistical MOS (SMOS) model accounts for both inter-die and intra-die variations.
T.B. Tarim, M. Ismail
openaire   +2 more sources

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A design for testability approach for nano-CMOS analogue integrated circuits

International Journal of Electronics, 2013
Dependability requirements must be considered from the beginning when designing safety-critical systems. Therefore, testing should even be considered earlier, intertwined with the design process. The process of designing for better testability is called design for testability (DfT).
Belgacem Hamdi, Ka Lok Man, Rached Tourki   +2 more
exaly   +2 more sources

A 0.35μm CMOS 200kHz–2GHz Fully-Analogue Closed-Loop Circuit for Continuous-Time Clock Duty-Cycle Correction in Integrated Digital Systems

2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018
In this work we present a fully-analogue Duty-Cycle Corrector (DCC) based on a closed-loop circuit topology operating a continuous-time 50% duty-cycle regulation of the generated output clock signal. In particular, a suitable feedback sub-system detects the duty-cycle values of the input and output clock signals and provides a corresponding control ...
De Marcellis A., Faccio M., Palange E.
openaire   +1 more source

Realistic faults mapping scheme for the fault simulation of integrated analogue CMOS circuits

Proceedings International Test Conference 1996. Test and Design Validity, 2002
A new fault modelling scheme for integrated analogue CMOS circuits referred to as Local Layout Realistic Fault Mapping is introduced. It is aimed at realistic fault assumptions prior to the final layout by investigating typical "local" layout structures of analogue designs.
openaire   +1 more source

The influence of No Fault Found in analogue CMOS circuits [PDF]

, 2014
The most difficult fault category in electronic systems is the “No Fault Found‿ (NFF). It is considered to be the most costly fault category in, for instance, avionics.
Jinbo Wan, Hans G Kerkhoff
exaly   +2 more sources

A Design Methodology for Analogue CMOS Circuits

, 2005
Summary form only given. The design of CMOS analogue circuits calls for the appraisal of transistor geometries and currents to meet prescribed specifications like gain-bandwidth, min. power consumption, etc. Design methodologies to this effect are scarce.
SBCCI 2005. 18th Symposium on Integrated Circuits and Systems Design, Jespers, Paul   +1 more
exaly   +1 more source

<title>Linearisation for analogue optical links using integrated CMOS predistortion circuits</title>

SPIE Proceedings, 2005
Fu-Chuan Lin, David M. Holburn
openaire   +1 more source