Results 231 to 240 of about 74,167 (345)

Analysis of dc and ac anomalous latch-up effects in commercial CMOS integrated circuits

, 1991
E. Zanoni, G. Spiazzi, B. Bonati, C. Canali, Paolo Pavan   +4 more
openalex   +1 more source

Survey of key technologies on millimeter-wave CMOS integrated circuits

, 2018
Fei Yu, Lei Gao, Lixiang Li, Shuo Cai, Wei Wang, Chunhua Wang   +5 more
openalex   +1 more source

Parametric Analysis of Spiking Neurons in 16 nm Fin Field‐Effect Transistor Technology

Advanced Intelligent Discovery, EarlyView.
Energy efficient computing has driven a shift toward brain‐inspired neuromorphic hardware. This study explores the design of three distinct silicon neuron topologies implemented in 16 nm fin field‐Effect transistor technology. While the Axon‐Hillock design achieves gigahertz throughput, its functional fragility persists. The Morris–Lecar model captures
Logan Larsh, Raiyan Siddique, Sarah S. Sharif, Yaser Mike Banad   +3 more
wiley   +1 more source

Low power and high-speed quadrate node upset tolerant latch design using CNTFET. [PDF]

Sci Rep
Asiya S, S SK.
europepmc   +1 more source

CMOS RF integrated circuits: past, present and future (invited)

, 1999
ThomasH . Lee
openalex   +1 more source

Dual‐Mode Oscillations in SiOx‐Based Threshold Switching Devices for Unconventional Probabilistic Computing

Advanced Intelligent Discovery, EarlyView.
To enable versatile unconventional computing, a single SiOx threshold switching device is engineered to exhibit controllable dual‐mode oscillation. By modulating the input voltage, the device selectively provides stable full oscillation for oscillatory neural networks and stochastic probabilistic oscillation for probabilistic bits and true random ...
Hyeonsik Choi, Jihyun Kim, Yonghun Kim, Jiyong Woo   +3 more
wiley   +1 more source

In-Sensor-Memory Computing for Post-Von Neumann Intelligence: A Perspective. [PDF]

Nanomicro Lett
Tang H, Yu N, Min P, Guo R, Zhang G.
europepmc   +1 more source

Hardware‐Based On‐Chip Learning Using a Ferroelectric AND‐Type Array With Random Synaptic Weights

Advanced Intelligent Systems, EarlyView.
This work demonstrates an energy‐efficient on‐chip learning system using an Metal‐Ferroelectric‐Insulator‐Semiconductor FeAND synaptic array. By employing a feedback alignment scheme with a separate backward array using fixed random weights, the system overcomes directional limitations of AND‐type arrays and achieves robust, low‐power learning suitable
Minsuk Song, Changhyeon Han, Joonhyeok Choi, Jongwoo Lee, Hyun‐min Kim, Wongi Hong, Ujin Kim, Sung‐Tae Lee, Daewoong Kwon   +8 more
wiley   +1 more source

Photoelectrochemical Oxidation and Etching Methods Used in Fabrication of GaN-Based Metal-Oxide-Semiconductor High-Electron Mobility Transistors and Integrated Circuits: A Review. [PDF]

Micromachines (Basel)
Lee CT, Lee HY.
europepmc   +1 more source

Subharmonic Mixers in CMOS Microwave Integrated Circuits

, 2009
Bradley Jackson
openalex   +1 more source