Results 201 to 210 of about 2,277 (292)

Improvement in Random Noise for Pixel-Parallel Single-Slope ADC with Consideration of Flicker Noise Effect. [PDF]

open access: yesSensors (Basel)
Uno M   +14 more
europepmc   +1 more source

An analytical model for the CMOS inverter

2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2014
A new analytical model for the CMOS inverter is introduced. This model results by solving analytically the differential equation which describes the inverter operation. It uses new simplified transistor current expressions which are developed taking into account the nanoscale effects and also considering temperature as a parameter.
P. Chaourani   +5 more
openaire   +2 more sources

High-Performance CMOS Inverter Array with Monolithic 3D Architecture Based on CVD-Grown n-MoS2 and p-MoTe2.

Small, 2023
In this work, monolithic three-dimensional complementary metal oxide semiconductor (CMOS) inverter array has been fabricated, based on large-scale n-MoS2 and p-MoTe2 grown by the chemical vapor deposition method.
Xionghui Jia   +9 more
semanticscholar   +1 more source

Demonstration of a Stacked CMOS Inverter at 60nm Gate Pitch with Power Via and Direct Backside Device Contacts

International Electron Devices Meeting, 2023
A device architecture with n-MOS and p-MOS transistors stacked on top of each other is considered a key option to continue scaling in the semiconductor industry.
M. Radosavljevic   +46 more
semanticscholar   +1 more source

Development of Knowledge-Based Artificial Neural Networks for Analysis of PSIJ in CMOS Inverter Circuits

IEEE transactions on microwave theory and techniques, 2023
In this article, a knowledge-based artificial neural network (ANN) is developed for predicting jitter in CMOS inverter circuits in the presence of power supply noise (PSN). The proposed ANN provides for efficient training in a hybrid approach using input
Ahsan Javaid, R. Achar, J. Tripathi
semanticscholar   +1 more source

0.5 V CMOS inverter-based tunable transconductor

Analog Integrated Circuits and Signal Processing, 2012
A new technique for CMOS inverter-based tunable transconductors is proposed in this paper. The proposed technique employs the master---slave approach and offers large transconductance tuning range using a control current. The transconductor was designed using triple-well 0.13 μm CMOS process under the ultra low supply voltage of 0.5 V.
S. Vlassis
openaire   +2 more sources

Fermi‐Level Pinning Free High‐Performance 2D CMOS Inverter Fabricated with Van Der Waals Bottom Contacts

Advanced Electronic Materials, 2021
Effective control of 2D transistors polarity is a critical challenge in the process for integrating 2D materials into semiconductor devices. Herein, a doping‐free approach for developing tungsten diselenide (WSe2) logic devices by utilizing the van der ...
Tien Dat Ngo   +9 more
semanticscholar   +1 more source

Performance Improvement for Ge FinFET CMOS Inverter With Supercritical Fluid Treatment

IEEE Electron Device Letters, 2022
Performance improvement on Ge nFinFET, pFinFET and CMOS inverter can be achieved by using a novel low temperature damage-free supercritical phase fluid (SCF) treatment.
D. Ruan   +9 more
semanticscholar   +1 more source

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