Results 211 to 220 of about 2,277 (292)

Variation Aware Timing Model of CMOS Inverter for an Efficient ECSM Characterization

IEEE International Symposium on Quality Electronic Design, 2021
In static timing analysis (STA), delay estimation of CMOS standard cells is accomplished by the effective current source model (ECSM) characterization method.
Lomash Chandra Acharya, A. Sharma, Venkatraman Ramakrishnan, Ajoy Mandal, S. Dasgupta, B. Anand   +5 more
semanticscholar   +1 more source

High-quality stacked CMOS inverter

IEEE Electron Device Letters, 1990
A stacked CMOS technology with enhanced device performance and small geometries is discussed. Surface-channel mobilities were measured to be 700 cm/sup 2//V-s for bulk n-channel devices and 165 cm/sup 2//V-s for the top PMOS transistors. Excellent subthreshold slope of 100 mV/decade and leakage currents below 150-fA/ mu m channel width were measured ...
R.P. Zingg, B. Hofflinger, G.W. Neudeck
openaire   +1 more source

Analytical transient response of CMOS inverters

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 1992
A general formula relating the waveform at the output of a CMOS inverter to the waveform at its input is derived. The formula is applied to three cases: a step input, a ramp input, and an exponential input. A one-dimensional function dependence of the inverter propagation delay and output slew rate on circuit parameters is derived and an inverter ...
A.I. Kayssi, K.A. Sakallah, T.M. Burks
openaire   +1 more source

Reliability study of 90nm CMOS inverter

2010 International Conference on Enabling Science and Nanotechnology (ESciNano), 2010
It is well-known that the miniaturization or scaling down process of integrated circuits (ICs) has lead to the reliability issues such as Hot-Carrier (HC) and Negative Bias Temperature Instability (NBTI) effects which are very significant on p-type MOSFET.
Dayanasari Abdul Hadi, Norhayati Soin, S.F. Wan Muhamad Hatta   +2 more
openaire   +1 more source

First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications

International Electron Devices Meeting, 2019
For the first time, CMOS inverters and 6T-SRAM cells based on vertically stacked gate-all-around complementary FETs (CFETs) are experimentally demonstrated.
S. Chang, J. Li, M.-K. Huang, Y. Huang, Stella Huang, H.C. Wang, Y. Huang, J.-Y. Wang, L. Yu, Y.-F. Huang, F. Hsueh, P. Sung, C. Wu, W. C. Ma, K. Kao, Y. J. Lee, C.-L. Lin, R. Chuang, K. Huang, S. Samukawa, Y. Li, W. Lee, T. Chu, T. Chao, G. W. Huang, W. Wu, J. Y. Li, J. Shieh, W. Yeh, Y. Wang, D. Lu, C. Wang, N. Lin, C. Su, S. Lo, H.-F. Huang   +35 more
semanticscholar   +1 more source

New CMOS inverter-based voltage multipliers

2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC), 2010
Four new CMOS inverter-based voltage multipliers consisted of PMOS/NMOS pass transistors, inverter circuits, and capacitors are proposed in the paper. The proposed voltage multipliers which combine the functions of rectifiers and charge-pumps improve the power conversion efficiency and reduce the number of passive components therefore they are suitable
null Ho-Cheng Lin, null Dong-Shiuh Wu, null Che-Min Kung, null Yuh-Shyan Hwang, null Jiann-Jong Chen   +4 more
openaire   +1 more source

Design of the CMOS inverter‐based amplifier: A quantitative approach

International journal of circuit theory and applications, 2019
The CMOS inverter can be used as an amplifier if properly biased in the transition region of its voltage‐transfer characteristics (VTC). In this paper, the design of this amplifier is investigated with its merits and demerits illustrated and with the ...
S. Sharroush
semanticscholar   +1 more source

Gate dielectric degradation in CMOS inverters

Microelectronic Engineering, 2009
To study the gate oxide degradation under stress conditions closer to the actual operation of devices in circuits, in this work, CMOS inverters have been stressed using DC and pulsed signals at the input. Uniform and non-uniform Fowler-Nordheim and Channel Hot Carrier stresses have been identified as those governing the oxide degradation, depending on ...
MARTIN MARTINEZ J, GERARDIN, SIMONE, RODRIGUEZ R, NAFRIA M, AYMERICH X, PACCAGNELLA, ALESSANDRO, GHIDINI G.   +6 more
openaire   +1 more source

Fifty Applications of the CMOS Inverter—Part 1 [The Analog Mind]

IEEE Solid-State Circuits Magazine
The CMOS inverter dates back to a patent filed by Wanlass in 1963 [1]. Shown in Figure 1 is the disclosed structure. (Unlike today’s convention, Wanlass denotes the drains by arrows.) With the scaling of the supply voltage in nanometer technologies, the ...
Behzad Razavi
semanticscholar   +1 more source

Modified CMOS inverters

Microelectronics Journal, 1983
Inverters with voltage controlled threshold at a constant supply voltage have been obtained by connecting a MOS transistor to the basic CMOS inverter source circuit. Control is exercised through the additional transistor's gate. Modified inverters with three and four transistors are described.
openaire   +1 more source