Results 231 to 240 of about 2,277 (292)
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Single InAs/GaSb Nanowire Low-Power CMOS Inverter
Nano Letters, 2012III-V semiconductors have so far predominately been employed for n-type transistors in high-frequency applications. This development is based on the advantageous transport properties and the large variety of heterostructure combinations in the family of III-V semiconductors.
Anil W, Dey +4 more
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Four-quadrant Analog Multiplier Based On CMOS Inverters
Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006., 2006In the article a new implementation of four-quadrant analog multiplier in CMOS technology is proposed. The circuit is based exclusively on CMOS inverters (or similar two-transistor blocks) and operates using quarter square technique. The outstanding feature of the circuit is an extreme suitability for low voltage operation and full compatibility with ...
Witold Machowski +2 more
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“The CMOS Inverter” as a Comparator in ADC Designs
Analog Integrated Circuits and Signal Processing, 2004This paper introduces a single-ended non-offset-cancelled flash ADC architecture, the “Threshold Inverter Quantizer” (TIQ). The TIQ is based on a CMOS inverter cell, in which the voltage transfer characteristics (VTC) are changed by systematic transistor sizing. As a result, a significant improvement of speed and reduction of area and power consumption
Tangel, Ali, Choi, Kyusun
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1992
Complementing a logical variable A to give Ā is accomplished using a basic inverter circuit. A standard CMOS inverter is quite simple and is built using two opposite-polarity MOSFETs in a complementary manner. The circuit gives a large output voltage swing and only dissipates significant power when the input is switched; these are two important ...
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Complementing a logical variable A to give Ā is accomplished using a basic inverter circuit. A standard CMOS inverter is quite simple and is built using two opposite-polarity MOSFETs in a complementary manner. The circuit gives a large output voltage swing and only dissipates significant power when the input is switched; these are two important ...
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Pseudocollector effect in a CMOS inverter
IEEE Transactions on Electron Devices, 1987The pseudocollector effect in a CMOS inverter is demonstrated by analyzing the current distribution in the latchup state. The decoupling of the current flow from the latchup feedback loop is controlled by the input voltage applied to the gates of n- and p-channel MOSFET's, which results in a reduction of latchup susceptibility.
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Design of CMOS Inverter and Chain of Inverters Using Neural Networks
2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), 2018This paper employs a model based on Artificial Neural Networks (ANN) to design a CMOS Inverter and Chain of Inverters and determine how accurately the ANN based designs are able to model the complex, non-linear problem of circuit design. ANN is designed to predict the performance parameters of a CMOS Inverter and chain of inverters for a given process ...
Likhit Valavala +2 more
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Accurate timing model for the CMOS inverter
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 2002This paper introduces an accurate, analytical timing model for the CMOS inverter. Analytical output waveform expressions for all the inverter operation regions and input waveform slopes are derived, which take into account the complete expression of the short-circuit current and the gate-to-drain coupling capacitance.
L. Bisdounis +3 more
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Transconductance CMOS inverter based AC coupling amplifier
2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS), 2014An AC-coupling technique based on the complementary MOS inverter is presented in this paper. The proposed technique employs a coupling capacitance, a reference inverter and two transistors in resistive mode of operation. As an application, a threes stage amplifier has been realized in 0.35μm CMOS process.
Herve Barthelemy +3 more
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Programmable Floating-Gate Techniques for CMOS Inverters
2005 IEEE International Symposium on Circuits and Systems, 2005The use of analog floating-gate elements in analog circuit research has steadily increased. These elements have great potential because they can be fabricated on a standard process and are low-power. An interesting application for these circuits is in the tuning of digital circuits for threshold and power consumption, which has been traditionally done ...
B.P. Degnan, R.B. Wunderlich, P. Hasler
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Stacked CMOS inverter with symmetric device performance
International Technical Digest on Electron Devices Meeting, 2003Summary form only given. An inherently crystalline monolithic three-dimensional CMOS process was developed. A stacked inverter was built with the footprint of a single transistor. The PMOS transconductance was raised by full-depletion and dual-gate control to match that of an NMOS transistor with the same geometry.
R.P. Zingg, B. Hofflinger, G.W. Neudeck
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