Results 241 to 250 of about 2,277 (292)

CMOS gate modeling based on equivalent inverter

ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349), 2003
A method for modeling complex CMOS gates by the reduction of each gate to an effective equivalent inverter is introduced. The conducting and parasitic behavior of parallel and serially connected transistors is accurately analyzed and an equivalent transistor is extracted for each case, taking into account the actual operating conditions of each device ...
A. Chatzigeorgiou, S. Nikolaidis, I. Tsoukalas, O. Koufopavlou   +3 more
openaire   +1 more source

Design-oriented delay model for CMOS inverter

2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI), 2012
This paper presents a new design oriented model for estimating the delay of a CMOS inverter. The model considers the impact of input transition time, input-to-output coupling capacitance, and physical effects such as drain-induced barrier lowering (DIBL) and velocity saturation. Thus, it is quite suitable for nanometer technologies.
Felipe S. Marranghello, Andre I. Reis, Renato P. Ribas   +2 more
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High Speed Ultra Low Voltage CMOS inverter

2008 IEEE Computer Society Annual Symposium on VLSI, 2008
In this paper we discuss timing details and performance of the ultra low voltage (ULV) logic style. The ULV logic gates can be utilized to design high speed systems operating at ultra low supply voltages. By imposing offsets to semi-floating-gate nodes the current level may be increased while maintaining a very low supply voltage.
Yngvar Berg, Omid Mirmotahari, Johannes Goplen Lomsdalen, Snorre Aunet   +3 more
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Efficient CMOS Invertible Logic Using Stochastic Computing

IEEE Transactions on Circuits and Systems I: Regular Papers, 2019
Invertible logic can operate in one of two modes: 1) a forward mode, in which inputs are presented and a single, correct output is produced, and 2) a reverse mode, in which the output is fixed and the inputs take on values consistent with the output. It is possible to create invertible logic using various Boltzmann machine configurations.
Sean C. Smithson, Naoya Onizawa, Brett H. Meyer, Warren J. Gross, Takahiro Hanyu   +4 more
openaire   +1 more source

A polyphase filter based on CMOS inverters

2005 NORCHIP, 2005
A new idea for generation of quadrature signals on chip is presented. The topology is based on a passive RC polyphase filter, where the resistive parts are made active by using inverters. The active filter combines quadrature generation, isolation, and gain without losing quadrature performance compared to a regular RC polyphase filter.
Fredrik Tillman, Henrik Sjöland
openaire   +1 more source

Offset cancellation of CMOS inverter comparators

2006
Comparators are main building blocks of the Nyquist rate and oversampled PCM ADCs and Sigma-Delta Modulation converters. There are three basic comparator architectures: high gain amplifier, charge balancing or data-sampling, and regenerative or latched comparators.
Matić, Tomislav, Švedek, Tomislav, Raguž, Krešimir   +2 more
openaire   +2 more sources

Development of A 4H-SiC CMOS Inverter

MRS Proceedings, 2006
AbstractIn this paper we report the first 4H-SiC CMOS inverter, which was designed to be integrated in the process flow of a 4H-SiC power DMOSFET. The channels of both of the n channel and p-channel MOSFETs of the inverter were 50 um wide by 3 um long.
Brett Adam Hull, Sei-Hyung Ryu, Husna Fatima, Jim Richmond, John W. Palmour, James Scofield   +5 more
openaire   +1 more source

Behavior of CMOS inverters at cryogenic temperatures

Solid-State Electronics, 1985
Abstract The switching times of six commercially available CMOS inverters have been measured as a function of temperature between 10 and 300 K. A ring oscillator was used in conjunction with a timing circuit allowing the measurements to be made during 60 ms thereby avoiding heating of the chips.
J. Laramée, M.J. Aubin, J.D.N. Cheeke
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Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas

IEEE J. Solid State Circuits, 1990
Ieee TAKAYASU SAKURAI MEMBER, Ieee A. RICHARD NEWTON FELLOW   +1 more
semanticscholar   +1 more source

Novel CMOS-Inverter Based VGA and VCRO

2018 International Japan-Africa Conference on Electronics, Communications and Computations (JAC-ECC), 2018
In this paper, a novel variable-gain amplifier (VGA) and a novel voltage-controlled ring oscillator (VCRO) are proposed. The two proposed schemes depend on the same controlled inverter unit with a single added device. The relationship between the voltage gain of the proposed VGA and the control voltage and the relationship between the oscillation ...
openaire   +1 more source