Results 111 to 120 of about 251 (146)
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Interleaver Design for Serial Concatenated Convolutional Codes
IEEE Communications Letters, 2004In this paper, we present an interleaver design method for SCCC. Our design criterion is to minimize the message-round probability in the SCCC graph which is specially well suited for SCCC. The message-round probability characterizes the message flow in the SCCC graph. By minimizing it, we can get a large interleaving gain.
Jungpil Yu +4 more
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Design of interleavers for turbo codes: iterative interleaver growth algorithms of polynomial complexity [PDF]
This paper addresses the problem of designing interleavers for parallel concatenated convolutional codes (PCCC's) tailored to specific constituent codes.
F Daneshgaran, M Mondin
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Blind identification of convolutional interleaver parameters
2009 7th International Conference on Information, Communications and Signal Processing (ICICS), 2009Blind identification of parameters in block interleaving has been studied by some researchers. In this paper, we extend the identification algorithm to convolutional type of interleaving. In particular, our algorithm is able to blindly determine the interleaver period, interleaver depth, number of stages in each shift register of interleaver and thus ...
Liru Lu, Kwok Hung Li, Yong Liang Guan
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Blind Estimation of Convolutional Interleaver Parameters
2012 8th International Conference on Wireless Communications, Networking and Mobile Computing, 2012Interleaving, an important technique in digital wireless communications systems, is commonly used to improve robustness against burst errors because it provides a form of time diversity. The unitive mathematical model of the convolutional interleaver was presented for the first time and the blind estimation of convolutional interleaving parameters has ...
Yong-qiang Jia +3 more
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Convolutional interleavers for stream-oriented parallel concatenated convolutional codes
Proceedings. 1998 IEEE International Symposium on Information Theory (Cat. No.98CH36252), 2002The design of convolutional interleavers (CIs) is considered for a stream-oriented parallel concatenated convolutional coding (PCCC). Design rules are developed for CIs using analysis of the interleaving equations as well as simulation results. Results show that CIs are viable design options which can offer improved performance for low latency designs ...
E.K. Hall, S.G. Wilson
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Interleaver optimization of convolutional turbo code for 802.16 systems
IEEE Communications Letters, 2009Convolutional turbo code (CTC) has been adopted as an optional channel coding scheme for wireless metropolitan area networks (WMAN) and digital video broadcasting (DVB) owing to its powerful error correction capability and flexibility. In spite of the fact that the internal interleaver of CTC mainly affects the characteristics of the code, interleaving
Sung-Joon Park, Jun-Ho Jeon
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Interleaving for outer convolutional codes in DS-CDMA systems
IEEE Transactions on Communications, 2000Summary: The paper deals with coding for direct-sequence code-division multiple-access (DS-CDMA) channels. A novel method for interleaver design is introduced that significantly improves the probability of error on Gaussian multiple-access channels.
Brück, Stefan +3 more
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On the Parallelism of Convolutional Turbo Decoding and Interleaving Interference.
2006In forward error correction, convolutional turbo codes were introduced to increase error correction capability approaching the Shannon bound. Decoding of these codes, however, is an iterative process requiring high computation rate and latency. Thus, in order to achieve high throughput and to reduce latency, crucial in emerging digital communication ...
Muller, Olivier +2 more
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Interleaved Concatenations of Polar Codes With BCH and Convolutional Codes
IEEE Journal on Selected Areas in Communications, 2016We analyze interleaved concatenation schemes of polar codes with outer binary BCH codes and convolutional codes. We show that both BCH-polar and Conv-polar codes can have a frame error rate that decays exponentially with the code length for all rates up to capacity, which is a substantial improvement in the error exponent over stand-alone polar codes ...
Ying Wang +2 more
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Viterbi decoder architecture for interleaved convolutional code
Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, 2002., 2003Sn area efficient high speed Veterbi decoder architecture, which is based on the state-parallel architecture with register exchange path memory structure, for interleaved convolutional code is proposed By replacing each delay (or storage) element in state metrics memory (or path metrics memory) and path memory (or survival memory) with I delays ...
null Jun Jin Kong, K.K. Parhi
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