Results 11 to 20 of about 2,995 (199)
In order to solve the problem of limited linearity and frame rate in the large array infrared (IR) readout integrated circuit (ROIC), a high-linearity and high-speed readout method based on adaptive offset compensation and alternating current (AC ...
Zhongjie Guo +4 more
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A new method for on-chip random telegraph noise (RTN) characteristic time constant extraction using the double sampling circuit in an 8.3 Mpixel CMOS image sensor is described.
Calvin Yi-Ping Chao +5 more
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It is difficult to measure the random telegraph noises (RTN) of MOSFET subthreshold currents at the sub-pA level directly and accurately. In this work, we used a charge integration method similar to the operation of the CMOS image sensors (CIS) to ...
Calvin Yi-Ping Chao +7 more
doaj +1 more source
This paper presents a low-noise reconfigurable sensor readout circuit with a multimodal sensing chain for voltage/current/resistive/capacitive microsensors such that it can interface with a voltage, current, resistive, or capacitive microsensor, and can ...
Donggeun You +10 more
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Capacitive sensing schemes are widely used for various microsensors; however, such microsensors suffer from severe parasitic capacitance problems. This paper presents a fully integrated low-noise readout circuit with automatic offset cancellation loop ...
Haryong Song +4 more
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This paper proposes a novel 12-bit column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for high-speed CMOS image sensors. Cooperating with the output offset storage (OOS) technique, a new correlated double sampling (CDS) is ...
Qihui Zhang +5 more
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A multi-function microelectromechanical system (MEMS) with a three-axis magnetometer (MAG) and three-axis accelerometer (ACC) function was implemented with an application-specific integrated circuit (ASIC)-compatible complementary metal-oxide ...
Chih-Hsuan Lin +2 more
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This paper presents an in-situ storage topology for ultra-high-speed burst mode imagers, enabling low noise operation while keeping a high frame depth.
Linkun Wu +7 more
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Area-efficient readout with 14-bit SAR-ADC for CMOS image sensors
This paper proposes a readout design for CMOS image sensors. It has been squeezed into a 7.5um pitch under a 0.28um 1P3M technology. The ADC performs one 14-bit conversion in only 1.5us and targets a theoretical DNL feature about +1.3/-1 at 14-bit ...
Aziza Sassi Ben, Dzahini Daniel
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The effects of X-ray irradiation on the random noises, especially the random telegraph noises (RTN), of a 45-nm on 65-nm stacked CMOS image sensor with 8.3M 1.1 μm pixels are investigated.
Calvin Yi-Ping Chao +8 more
doaj +1 more source

