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High-performance IP routing table lookup using CPU caching
IEEE INFOCOM '99. Conference on Computer Communications. Proceedings. Eighteenth Annual Joint Conference of the IEEE Computer and Communications Societies. The Future is Now (Cat. No.99CH36320), 1999Wire-speed IP (Internet Protocol) routers require very fast routing table lookup for incoming IP packets. The routing table lookup operation is time consuming because the part of an IP address used in the lookup, i.e., the network address portion, is variable in length.
T. Chiueh, P. Pradhan
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A CMOS RISC CPU with on-chip parallel cache
Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94, 2002This CMOS CPU in a 0.55 /spl mu/m, 3-metal process integrates over 1.2 M transistors on a single chip. All circuitry on-chip operates at 140 MHz under typical conditions. All off-chip interfaces are cycled at the same frequency (with the exception of system bus interface, which is cycled at 120 MHz). Chip parameters are given. >
E. Rashid +27 more
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Heterogeneous Cache Hierarchy Management for Integrated CPU-GPU Architecture
2019 IEEE High Performance Extreme Computing Conference (HPEC), 2019Unlike the traditional CPU-GPU heterogeneous architecture where CPU and GPU have separate DRAM and memory address space, current heterogeneous CPU-GPU architectures integrate CPU and GPU in the same die and share the same last level cache (LLC) and memory. For the two-level cache hierarchy in which CPU and GPU have their own private L1 caches but share
Hao Wen, Wei Zhang
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A Simple Cache Coherence Scheme for Integrated CPU-GPU Systems
2020 57th ACM/IEEE Design Automation Conference (DAC), 2020This paper presents a novel approach to accelerate applications running on integrated CPU-GPU systems. Many integrated CPU-GPU systems use cache-coherent shared memory to communicate. For example, after CPU produces data for GPU, the GPU may pull the data into its cache when it accesses the data.
Ardhi Wiratama Baskara Yudha +3 more
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Optimizing CPU cache performance for Pregel-like graph computation
2015 31st IEEE International Conference on Data Engineering Workshops, 2015In-memory graph computation systems have been used to support many important applications, such as PageRank on the web graph and social network analysis. In this paper, we study the CPU cache performance of graph computation. We have implemented a graph computation system, called GraphLite, in C/C++ based on the description of Pregel.
Songjie Niu, Shimin Chen
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MeshUp: Stateless Cache Side-channel Attack on CPU Mesh
2022 IEEE Symposium on Security and Privacy (SP), 2022Junpeng Wan +3 more
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CPU CACHE SHARING DETECTOR FOR C/C++ PROGRAMS
The International Conference on Security, Fault Tolerance, IntelligenceThe paper discusses the false-sharing detector and the SHERIFF-DETECT detector, as well as its modification to create a more modern tool that can be used, more flexible in terms of architectural dependencies and using modern processor instructions. The advantages and disadvantages of different false-sharing detector approaches are considered.
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