Results 81 to 90 of about 62,688 (226)
A Hybrid Architecture With Low Latency Interfaces Enabling Dynamic Cache Management
IEEE Access, 2018 The main focus of the dominant technologies in the high performance computation (HPC) market, such as GPU and multicore systems, is put on processing power, while much less attention has been paid to communication delays inside hybrid architectures.
Michel Gemieux +4 more
doaj +1 more source
Fast Longest Prefix Matching by Exploiting SIMD Instructions
IEEE Access, 2020 Longest prefix matching (LPM) is a fundamental process in IP routing used not only in traditional hardware routers but also in software middleboxes. However, the performance of LPM in software is still insufficient for processing packets at over 100 Gbps,
Yukito Ueno +3 more
doaj +1 more source
Hints on the Multicore CPU Design for Personal Computers
Acta Electrotechnica et Informatica, 2022 - Multi-core processors are created by combining multiple units, each called the core, containing the processing unit, registers and a cache. This study provides a detailed analysis on the performances of multicore CPUs for personal computers.
İren Ecem +2 more
doaj +1 more source
Design Principles for Scaling Multi-core OLTP Under High Contention
, 2016 Although significant recent progress has been made in improving the multi-core scalability of high throughput transactional database systems, modern systems still fail to achieve scalable throughput for workloads involving frequent access to highly ...
Abadi, Daniel J. +2 more
core +1 more source
Journal of Geophysical Research: Atmospheres, Volume 131, Issue 1, 16 January 2026.Abstract Hierarchical agglomerative clustering is a useful analysis technique which allows for a level of stability, interpretability and flexibility not available in other similar techniques such as K‐means, density‐based clustering or positive matrix factorization.
Colin J. Lee +2 more
wiley +1 more source
Performance analysis of partitioned caches in heterogeneous multi-core CPUs [PDF]
International Journal of Research in Advanced Electronics EngineeringDevi Venkatesh Gowtham, Sweta S Munnoli
openaire +2 more sources
, 2018 Intel Xeon Phi many-integrated-core (MIC) architectures usher in a new era of terascale integration. Among emerging killer applications, parallel graph processing has been a critical technique to analyze connected data.
Chen, Langshi, Jiang, Lei, Qiu, Judy
core +1 more source
Concurrency and Computation: Practice and Experience, Volume 38, Issue 1, January 2026.ABSTRACT The increasing availability of GPU accelerated architectures for high‐performance computing presents new opportunities for scientific software but also challenges due to the complexity of porting legacy codes to accelerator platforms. Directive‐based programming models such as OpenACC offer a minimally intrusive pathway to exploit GPU ...
Carlos Junqueira‐Junior +3 more
wiley +1 more source
Towards Workload‐Tailored Optimization of Job Scheduling Policies in HPC Environments
Concurrency and Computation: Practice and Experience, Volume 38, Issue 1, January 2026.ABSTRACT Supercomputers play a pivotal role in advancing research and development across diverse scientific and engineering domains. However, configuring job scheduling in these systems to ensure maximum productivity and cost‐effectiveness is a challenge. Workload simulation emerges as a crucial tool in this context, offering a mechanism to explore job
João Pedro M. N. dos Santos +2 more
wiley +1 more source
Automatic Loop Kernel Analysis and Performance Modeling With Kerncraft
, 2015 Analytic performance models are essential for understanding the performance characteristics of loop kernels, which consume a major part of CPU cycles in computational science.
Eitzinger, Jan +3 more
core +1 more source