Results 201 to 210 of about 2,568 (258)
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Partitioned and parallel cyclic redundancy checking
Proceedings of 36th Midwest Symposium on Circuits and Systems, 2002In this paper, the linear feedback shift register (LFSR) is redesigned to process several bits of a long data stream simultaneously in order to obtain a signature more quickly. The resulting structure is capable of encoding, decoding, detecting, and correcting errors in cyclic codes partitioned into variable length words; hence, it is given the name ...
A. Sobski, A. Albicki
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A self-timed cyclic redundancy check (CRC) in VLSI
Proceedings of 40th Midwest Symposium on Circuits and Systems. Dedicated to the Memory of Professor Mac Van Valkenburg, 1999A self-timed approach to implement a cyclic redundancy check (CRC) for the application of telecommunications is described. The approach is oriented toward multiple channel communications. The paper presents a new scheme to handle an asynchronous feedback to implement the CRC engine.
S.Henry Li, Charles A. Zukowski
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Cyclic Redundancy Checking (CRC) Accelerator for the FlexCore Processor
2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, 2010A proven approach to increase performance of general-purpose processors is to add hardware accelerators. In its basic configuration, the FlexCore processor has a limited set of datapath units. But thanks to a flexible datapath interconnect and a wide control word, the FlexCore datapath is explicitly designed to support integration of special units that,
Muhammad Waqar Azhar +2 more
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Cyclic redundancy checks with factorable generators
IEE Proceedings - Communications, 2003Applications are proposed for cyclic redundancy checks (CRCs) that have factorable rather than primitive generator polynomials. Suitable encoding and decoding methods are developed. Factored-generator CRCs are then compared with tandem CRCs that have an inner code and outer code. When the factors of the generator are used as the generators of the inner
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Construction of Cyclic Redundancy Check Codes for SDDC Decoding in DRAM Systems
IEEE Transactions on Circuits and Systems II: Express Briefs, 2023Jiho Kim +2 more
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An Adaptive Successive Cancellation List Decoder for Polar Codes with Cyclic Redundancy Check
IEEE Communications Letters, 2012David Tse
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Cyclic redundancy check code based high-rate error-detection code for perpendicular recording
IEEE Transactions on Magnetics, 2006Jaekyun Moon
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