Results 231 to 240 of about 1,028,038 (292)

Low-Complexity Parallel Cyclic Redundancy Check

2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021
Cyclic redundancy check (CRC) is adopted in many digital communication and storage systems to ensure data integrity. CRC en/decoding is carried out using linear feedback shift registers (LFSRs) and a parallel LFSR can be implemented by registers with a feedback matrix multiplication and an input pre-processing matrix multiplication. A large parallelism
Xinmiao Zhang 0001, Yok Jye Tang
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Cyclic redundancy checking by program

Proceedings of the May 16-18, 1972, spring joint computer conference on - AFIPS '72 (Spring), 1971
Recent advances in the use of mini-computers as control elements of a computer complex and as intelligent terminals are indicative of a trend toward relocation of certain hardware functions to micro-program or machine level program. One such function which is a particularly good candidate, for various reasons, has already been moved into program in ...
Paul E. Boudreau, Robert F. Steen
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Cyclic redundancy checks in Ada95

ACM SIGAda Ada Letters, 1997
Among the many error detection techniques used in (tele)communications, the Cyclic Redundancy Check (CRC) is probably the most powerful one. Roughly speaking the CRC is merely a modulo-2 division of the data (bits) to be transmitted by some 'magical' polynomial known for its high error detection capabilities.
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Cyclic redundancy checking

1997
While parity checks are useful for low data rates and asynchronous messages where large gaps in between successive bytes make compilation of data into block impossible, for more general protection of data a much more robust error detection scheme is necessary.
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Pipelined Cyclic Redundancy Check (CRC) Calculation

2007 16th International Conference on Computer Communications and Networks, 2007
Traditional methods to calculate CRC suffer from diminishing returns. Doubling the data width doesn't double the maximum data throughput, the worst case timing path becomes slower. Feedback in the traditional implementation makes pipelining problematic. However, the on chip data width used for high throughput protocols is constantly increasing.
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Partitioned and parallel cyclic redundancy checking

Proceedings of 36th Midwest Symposium on Circuits and Systems, 2002
In this paper, the linear feedback shift register (LFSR) is redesigned to process several bits of a long data stream simultaneously in order to obtain a signature more quickly. The resulting structure is capable of encoding, decoding, detecting, and correcting errors in cyclic codes partitioned into variable length words; hence, it is given the name ...
A. Sobski, A. Albicki
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A self-timed cyclic redundancy check (CRC) in VLSI

Proceedings of 40th Midwest Symposium on Circuits and Systems. Dedicated to the Memory of Professor Mac Van Valkenburg, 1999
A self-timed approach to implement a cyclic redundancy check (CRC) for the application of telecommunications is described. The approach is oriented toward multiple channel communications. The paper presents a new scheme to handle an asynchronous feedback to implement the CRC engine.
S.Henry Li, Charles A. Zukowski
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Cyclic Redundancy Checking (CRC) Accelerator for the FlexCore Processor

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, 2010
A proven approach to increase performance of general-purpose processors is to add hardware accelerators. In its basic configuration, the FlexCore processor has a limited set of datapath units. But thanks to a flexible datapath interconnect and a wide control word, the FlexCore datapath is explicitly designed to support integration of special units that,
Muhammad Waqar Azhar, Tung Thanh Hoang, Per Larsson-Edefors   +2 more
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Cyclic redundancy checks with factorable generators

IEE Proceedings - Communications, 2003
Applications are proposed for cyclic redundancy checks (CRCs) that have factorable rather than primitive generator polynomials. Suitable encoding and decoding methods are developed. Factored-generator CRCs are then compared with tandem CRCs that have an inner code and outer code. When the factors of the generator are used as the generators of the inner
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Quantum cyclic redundancy check codes.

CoRR, 2023
Ricard Vilar, Simeon Ball
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