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Implementation of Cyclic Redundancy Check in Data Recovery
2021 Second International Conference on Electronics and Sustainable Communication Systems (ICESC), 2021Cyclic Redundancy Check (CRC) technique can be widely used in data communication and storage devices in order to detect the sudden errors present in the data. The main motivation of this research was to detect the sudden, random or burst errors present in the transmission channels. This technique was very simple and easy to implement.
Nandivada Sridevi +2 more
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Partitioned and parallel cyclic redundancy checking
Proceedings of 36th Midwest Symposium on Circuits and Systems, 2002In this paper, the linear feedback shift register (LFSR) is redesigned to process several bits of a long data stream simultaneously in order to obtain a signature more quickly. The resulting structure is capable of encoding, decoding, detecting, and correcting errors in cyclic codes partitioned into variable length words; hence, it is given the name ...
A. Sobski, A. Albicki
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A self-timed cyclic redundancy check (CRC) in VLSI
Proceedings of 40th Midwest Symposium on Circuits and Systems. Dedicated to the Memory of Professor Mac Van Valkenburg, 1999A self-timed approach to implement a cyclic redundancy check (CRC) for the application of telecommunications is described. The approach is oriented toward multiple channel communications. The paper presents a new scheme to handle an asynchronous feedback to implement the CRC engine.
S.Henry Li, Charles A. Zukowski
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Cyclic redundancy checks in Ada95
ACM SIGAda Ada Letters, 1997Among the many error detection techniques used in (tele)communications, the Cyclic Redundancy Check (CRC) is probably the most powerful one. Roughly speaking the CRC is merely a modulo-2 division of the data (bits) to be transmitted by some 'magical' polynomial known for its high error detection capabilities.
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Cyclic Redundancy Checking (CRC) Accelerator for the FlexCore Processor
2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, 2010A proven approach to increase performance of general-purpose processors is to add hardware accelerators. In its basic configuration, the FlexCore processor has a limited set of datapath units. But thanks to a flexible datapath interconnect and a wide control word, the FlexCore datapath is explicitly designed to support integration of special units that,
Muhammad Waqar Azhar +2 more
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