Results 241 to 250 of about 37,653 (292)

On the cyclic redundancy-check codes with 8-bit redundancy

Computer Communications, 1998
Polynomials of degree eight over GF(2) which are suitable to be used as generator polynomials for cyclic redundancy-check (CRC) codes are investigated. Their minimum distance, properness and undetected error probability for binary symmetric channels (BSCs) are compared with the existing ATM standard.
Tsonka Baicheva, Stefan Dodunekov, Peter Kazakov   +2 more
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Finding cyclic redundancy check polynomials for multilevel systems

IEEE Transactions on Communications, 1998
Summary: This letter describes a technique for finding cyclic redundancy check polynomials for systems for transmission over symmetric channels that encode information in multiple voltage levels so that the resulting redundancy check gives good error protection and is efficient to implement. The codes that we construct have a Hamming distance of 3 or 4.
Davis, James A., Mowbray, Miranda, Crouch, Simon   +2 more
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Cyclic redundancy checking

1997
While parity checks are useful for low data rates and asynchronous messages where large gaps in between successive bytes make compilation of data into block impossible, for more general protection of data a much more robust error detection scheme is necessary.
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Cyclic redundancy checks with factorable generators

IEE Proceedings - Communications, 2003
Applications are proposed for cyclic redundancy checks (CRCs) that have factorable rather than primitive generator polynomials. Suitable encoding and decoding methods are developed. Factored-generator CRCs are then compared with tandem CRCs that have an inner code and outer code. When the factors of the generator are used as the generators of the inner
openaire   +1 more source

A RFID algorithm based on Cyclic Redundancy Check

2009 3rd International Conference on Anti-counterfeiting, Security, and Identification in Communication, 2009
In this paper, a novel anti-collision algorithm based on cyclic redundancy check is proposed to improve the performance of the RFID system. Compared with the previous algorithm, two new techniques can be found in our algorithm. First, noting transmitting the RN16 in the process of reading costs too much time in ISO18000–6C protocol, we use 16-bit ...
null Yan-Fei Li, null Hong-Jun Wang, null Hua Li   +2 more
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Pipelined Cyclic Redundancy Check (CRC) Calculation

2007 16th International Conference on Computer Communications and Networks, 2007
Traditional methods to calculate CRC suffer from diminishing returns. Doubling the data width doesn't double the maximum data throughput, the worst case timing path becomes slower. Feedback in the traditional implementation makes pipelining problematic. However, the on chip data width used for high throughput protocols is constantly increasing.
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Some transforms in cyclic redundancy check (CRC) computation

2011 International Conference on Electrical and Control Engineering, 2011
Some transforms in cyclic redundancy check (CRC) computation, such as the multiplication of two messages' polynomials, shift, complement, and different initial (defaulted) remainder of a message, are studied. The relationships of the CRCs between the transformed message and the original one are also addressed from the mathematical point of view.
Zhanqi Xu, Aijun Wen, Zengji Liu
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Error Correcting Cyclic Redundancy Checks based on Confidence Declaration

2006 6th International Conference on ITS Telecommunications, 2006
Cyclic redundancy check is one of the most popular methods of error detection for digital signals, whereas it has not the inherent capability of correcting multi-bit errors and most of the existing works focus on algorithm optimization of CRC. Take example for the Mode S downlink error correction, this paper investigates two multi-bit error correction ...
Chen Shi-yi, Li Yu-bai
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Parallel encoder, decoder, detector, corrector for cyclic redundancy checking

[Proceedings] 1992 IEEE International Symposium on Circuits and Systems, 2003
Redesigning the linear feedback shift register so that syndrome calculations can be performed in one sweep allows for fast error control in high-speed computer networks. The resulting structure forms the basis of the PEDDC (parallel encoder, decoder, detector, corrector) which replaces the conventional SEDDC (serial encoder, decoder, detector ...
A. Sobski, A. Albicki
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Realization of CRC (Cyclic Redundancy Check) Based on LabView

Applied Mechanics and Materials, 2014
Algorithm and characteristics of CRC were investigated, and a pipeline algorithm steps to achieve it was introduced. The Modbus protocol RTU mode with CRC-16 was developed based on LabView using two methods, embedded c statements and graphical language based on LabView2012.
Wei Gao, Zhong Tang
openaire   +1 more source