Implementasi Rangkaian CRC (Cyclic Redundancy Check) Generator pada FPGA (Field Programmable Gate Array) [PDF]
IJEIS (Indonesian Journal of Electronics and Instrumentation Systems), 2019 Data integrity in high speed data transmission process is a major requerment that can not be ignored. High speed data transmission is prone to data errors. CRC (Cyclic Redundancy Check) is a mechanism that is often used as a detector errors in data transmission and storage process.
Augoestien, Nia Gella, Aditya, Ryan
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Cyclic redundancy check-aided successive cancellation-based polar decoders [PDF]
, 2023 Research on channel coding for network transmission using polar codes has produced excellent results. By removing error redundancy from the decoding process, cyclic redundancy check (CRC) is frequently used by researchers to increase a system’s ...
Ezmin Abdullah +7 more
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Cyclic redundancy check-based detection algorithms for automatic identification system signals received by satellite. [PDF]
, 2013 This paper addresses the problem of demodulating signals transmitted in the automatic identification system. The main characteristics of such signals consist of two points: (i) they are modulated using a trellis-coded modulation, more precisely a ...
LeMaitre, Julia +11 more
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Cyclic Redundancy Checking (CRC) Accelerator for Embedded Processor Datapaths [PDF]
International Journal of Advanced Computer Science and Applications, 2017 We present the integration of a multimode Cyclic Redundancy Checking (CRC) accelerator unit with an embedded processor datapath to enhance the processor performance in terms of execution time and energy efficiency. We investigate the performance of CRC accelerated embedded processor datapath in terms of execution time and energy efficiency.
Abdul Rehman +4 more
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Design of concatenated Hash-Polar code based on segmented CRC code
Dianxin kexue, 2022 As a linear block code, the polarization code has a lower coding complexity and a definite structure, but when it has a short or medium code length, the performance will be reduced.A design method of concatenated HashPolar codes based on segmented cyclic
Zhengjie LI, Shunlan LIU, Xu ZHANG
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Energy efficient implementation of multi-phase quasi-adiabatic Cyclic Redundancy Check in near field communication [PDF]
, 2018 Ultra-low power operation in power-limited portable devices (e.g. cell phone and smartcard) is paramount. Existing conventional CMOS consume high energy. The adiabatic logic technique has the potential of rendering energy efficient operation.
Kale, I., Maheshwari, S., Bartlett, V.
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Exploring Various Levels of Parallelism in High-Performance CRC Algorithms
IEEE Access, 2019 Modern processors have increased the capabilities of instruction-level parallelism (ILP) and thread-level parallelism (TLP). These resources, however, typically exhibit poor utilization on conventional cyclic redundancy check (CRC) algorithms.
Mucong Chi, Dazhong He, Jun Liu
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Design of fieldbus chip based on IEC 1158 standard
Dianzi Jishu Yingyong, 2022 This paper introduces a kind of physical layer fieldbus chip architecture and its implementation in accordance with IEC 1158 standard. The chip is designed with Manchester codec circuit, Cyclic Redundancy Check(CRC) verification circuit, carrier ...
Zhang Liguo +5 more
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Design and implementation of parallel CRC algorithm for fibre channel on FPGA
The Journal of Engineering, 2019 Fibre channel (FC) provides the high-speed and low-latency communication between the end systems, widely used in data storage, aerospace applications and large electronic equipment including radar systems.
Wu Chuxiong, Shi Haifeng
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Area efficient parallel lfsr for cyclic redundancy check [PDF]
, 2020 Cyclic Redundancy Check (CRC), code for error detection finds many applications in the field of digital communication, data storage, control system and data compression.
Rita Mahajan +5 more
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