Results 201 to 210 of about 573,656 (267)
Nonvolatile phase-programmable spintronic terahertz emitter via laser-induced spin polarization switching. [PDF]
Natl Sci RevLiu S +12 more
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The cricket cercal system implements delay-line processing.
J Neurophysiol, 2010 Mulder-Rosi J, Cummins GI, Miller JP.
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Probing and controlling coherent and incoherent dynamics of phase transitions via multipulse excitation. [PDF]
Sci AdvGuo FW +6 more
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Hearing Research, 1987
A relatively simple circuit is described which delays audio signals in 5 microseconds steps from 0 microsecond to 4000 microseconds. Delays are programmed via twelve TTL-level data lines. The magnitude response is flat and the phase response is linear from DC to 5 kHz. The gain of the circuit is fixed and independent of the selected delay.
J L, Schiano, C, Trahiotis
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A relatively simple circuit is described which delays audio signals in 5 microseconds steps from 0 microsecond to 4000 microseconds. Delays are programmed via twelve TTL-level data lines. The magnitude response is flat and the phase response is linear from DC to 5 kHz. The gain of the circuit is fixed and independent of the selected delay.
J L, Schiano, C, Trahiotis
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On-line calibration for non-linearity reduction of delay-locked delay-lines
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483), 2002A reduction of the non-linearity of a CMOS all-digital shunt-capacitor delay-line is achieved by performing an on-line statistical test of the line and correcting the individual cell delay mismatch according to the test results. A fully digital cell controller efficiently implementing the calibration procedure has been realized. Simulation results show
BARONTI, FEDERICO +4 more
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Delay calibration circuit for delay lines
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015A circuit for delay calibration of delay lines has been proposed. The proposed circuit is attractive for forwarded-clock links. Novel delay cell and a clock conditioning block reduce startup and false lock problems. The proposed wide-range calibration circuit has been realized in a 28nm CMOS process.
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CORD: contention resolution by delay lines
IEEE Journal on Selected Areas in Communications, 1996The implementation of optical packet-switched networks requires that the problems of resource contention, signalling and local and global synchronization be resolved. A possible optical solution to resource contention is based on the use of switching matrices suitably connected with optical delay lines.
Imrich Chlamtac +14 more
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