Results 221 to 230 of about 5,559,122 (287)

Neural Markers of Reward Valuation and Impulsive Decision-Making in Mania Risk.

JAMA Psychiatry
Raeder R, Arora M, Jones N, Chase HW, Bertocci M, Roberts LT, Bebko G, Aslam HA, Graur S, Taylor M, Atkinson M, Benjamin O, Wang Y, Stiffler R, Phillips ML.   +14 more
europepmc   +1 more source

Effects of augmented feedback delay on neural correlates of feedback processing in motor practice. [PDF]

Exp Brain Res
Margraf L, Krause D, Maurer LK, Weigelt M.   +3 more
europepmc   +1 more source

Rod + cone signal interference impairs mesopic motion discriminability in a model circuit. [PDF]

J Vis
Songco-Aguas A, Rieke F, Gutierrez GJ.
europepmc   +1 more source

Underlying Causes and Preventability of Hospital-Onset Sepsis Events.

JAMA Netw Open
Manzoor F, Klompas M, Seetharaman S, Chan C, Rhee C.   +4 more
europepmc   +1 more source

On-line calibration for non-linearity reduction of delay-locked delay-lines

ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483), 2002
A reduction of the non-linearity of a CMOS all-digital shunt-capacitor delay-line is achieved by performing an on-line statistical test of the line and correcting the individual cell delay mismatch according to the test results. A fully digital cell controller efficiently implementing the calibration procedure has been realized. Simulation results show
BARONTI, FEDERICO, FANUCCI, LUCA, Lunardini D., RONCELLA, ROBERTO, SALETTI, ROBERTO   +4 more
openaire   +3 more sources

Tunable delay line arrangement

, 2013
A tunable chirped delay line arrangement (0) configured to operatively propagate a signal and includes a at least one chirped delay line (1) arranged along a reference direction (z) on a dielectric layer (2) arranged on a ground plane (3).
GEVORGYAN SPARTAK, OLSSON BENGT-ERIK
core   +4 more sources

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A programmable-delay line

Hearing Research, 1987
A relatively simple circuit is described which delays audio signals in 5 microseconds steps from 0 microsecond to 4000 microseconds. Delays are programmed via twelve TTL-level data lines. The magnitude response is flat and the phase response is linear from DC to 5 kHz. The gain of the circuit is fixed and independent of the selected delay.
J L, Schiano, C, Trahiotis
openaire   +2 more sources

Delay calibration circuit for delay lines

2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015
A circuit for delay calibration of delay lines has been proposed. The proposed circuit is attractive for forwarded-clock links. Novel delay cell and a clock conditioning block reduce startup and false lock problems. The proposed wide-range calibration circuit has been realized in a 28nm CMOS process.
openaire   +2 more sources