Results 41 to 50 of about 875,510 (306)
Hot-carrier-induced deep-level defects from gated-diode measurements on MOSFETs [PDF]
, 1990 The reverse-bias current in the gated-diode configuration of hot-carrier degraded MOS devices was measured. It is shown that interface defects created by the degradation contribute predominantly to the generation current.
Asenov, A. +4 more
core +1 more source
Advanced Engineering Materials, Volume 27, Issue 6, March 2025.ErB4 and NdB4 nanostructured powders are produced by mechanochemical synthesis. 5 h mechanical alloying and 4 M HCl acid leaching are used in the production. ErB4 and NdB4 powders exhibit maximum magnetization of 0.4726 emu g−1 accompanied with an antiferromagnetic‐to‐paramagnetic phase transition at about TN = 18 K and 0.132 emu g−1 with a maximum at ...
Burçak Boztemur +5 more
wiley +1 more source
Results in Surfaces and InterfacesGraphene derivatives, with their exceptional mobility and tunable optical bandgap, have emerged as promising candidates as interfacial layers, particularly as hole transport layers (HTLs) in bulk heterojunction organic solar cells (BHJOSCs).
Denet Davis, K.S. Sudheer
doaj +1 more source
Sensors, 2023 Clinical alarm and decision support systems that lack clinical context may create non-actionable nuisance alarms that are not clinically relevant and can cause distractions during the most difficult moments of a surgery. We present a novel, interoperable,
David Arney +5 more
doaj +1 more source
Optimization of Excitation in FDTD Method and Corresponding Source Modeling [PDF]
, 2015 Source and excitation modeling in FDTD formulation has a significant impact on the method performance and the required simulation time. Since the abrupt source introduction yields intensive numerical variations in whole computational domain, a generally ...
Aleksic, S. +3 more
core +2 more sources
Planar Solid‐State Nanopores Toward Scalable Nanofluidic Integration Based on CMOS Technology
Advanced Engineering Materials, EarlyView.We present a scalable silicon‐based fabrication strategy for planar solid‐state nanopores to enable their integration with complex nanofluidic systems. Prototype devices demonstrate normal voltage‐current characteristics, good noise performance, and appreciable streaming currents. Our CMOS‐compatible fabrication process offers precise geometric control
Ngan Hoang Pham +7 more
wiley +1 more source
East European Journal of PhysicsA growing area of research in recent years has focused on improving the efficiency of [6,6]-phenyl-C61-butyric acid methyl ester (PCBM) fullerene-based bulk heterojunction organic solar cells (BHJOSC) using poly 3-hexylthiophene-2,5-diyl (P3HT) as the ...
Denet Davis, K.S. Sudheer
doaj +1 more source
Process Variability—Technological Challenge and Design Issue for Nanoscale Devices
Micromachines, 2018 Current advanced transistor architectures, such as FinFETs and (stacked) nanowires and nanosheets, employ truly three-dimensional architectures. Already for aggressively scaled bulk transistors, both statistical and systematic process variations have ...
Jürgen Lorenz +6 more
doaj +1 more source
Clocked Magnetostriction-Assisted Spintronic Device Design and Simulation
, 2017 We propose a heterostructure device comprised of magnets and piezoelectrics that significantly improves the delay and the energy dissipation of an all-spin logic (ASL) device.
Dutta, Sourav +7 more
core +1 more source
Layout to circuit extraction for three-dimensional thermal-electrical circuit simulation of device structures [PDF]
, 1996 In this paper, a method is proposed for extraction of coupled networks from layout information for simulation of electrothermal device behavior. The networks represent a three-dimensional (3-D) device structure with circuit elements.
Bosma, A. +3 more
core +3 more sources