Results 241 to 250 of about 260,602 (285)
38th Electronics Components Conference 1988., Proceedings., 2003 A photodefinable polyimide based on 3,3',4,4'-benzophenone tetracarboxylic dianhydride, oxydianiline, and metaphenylene-diamine (BTDA-ODA-MPD) was studied for its application as a stress buffer film over the passivation in a plastic-encapsulated device.
H. Fatemi, T.S. Tarter, M.M. Khan
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2018 19th International Conference of Young Specialists on Micro/Nanotechnologies and Electron Devices (EDM), 2018 This work represents results obtained during research of high frequency IC packaging. The interface between IC die and PCB is described and its inner structure is developed: contact pads on IC die, bondwires and chip outputs. As an example of method developed the interface effects into device development and characteristics are shown for the LNA module
Igor K. Surin, Andrey A. Antonov
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Thermal impact of extreme die thinning in bump-bonded three-dimensional integrated circuits
Microelectronics Reliability, 2017 Abstract In three-dimensional integrated circuits (3DICs) aggressive wafer-thinning can lead to large thermal gradients, including spikes in individual device temperatures. In a non-thinned circuit, the large bulk silicon wafer on which devices are built works as a very good thermal conductor, enabling heat to diffuse laterally.
Haruo Shimamoto +5 more
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A die-on-board PCB for testing high-speed integrated circuits
2015 IEEE Applied Electromagnetics Conference (AEMC), 2015 Chip-on-board (COB) printed circuit boards (PCB) appear to be a very attractive solution for testing high-speed integrated circuits (IC). Attaching the bare die directly on a PCB takes away the packaging cost, which is as high as the chip fabrication cost or more when it comes to the high-speed ICs. Wafer probing is a good alternative, but may not come
Mukul Ratwani +3 more
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Advances in Electronic Packaging, Parts A, B, and C, 2005 This paper presents a method of finite element analysis for calculating moisture concentration in non-isothermal and non-steady states of moisture for integrated circuit packages composed of dissimilar moisture-permeable materials. The method can address non-Fickian behavior of materials in moisture diffusivity.
Hiroyuki Tanaka, Takashi Numata
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CMOS Sensor Arrays for High Resolution Die Stress Mapping in Packaged Integrated Circuits
IEEE Sensors Journal, 2013 This paper reports the design, calibration and application of multiplexed arrays of piezoresistive field-effect transistor stress sensors fabricated in a standard complementary-metal-oxide semiconductor (CMOS) process. Two complementary arrays of 256-current mirror sensor cells provide high spatial density stress mapping with approximately 300 pts/mm2 ...
Yonggang Chen +2 more
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2018 15th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON), 2018 In this paper, installation automatic die bonding machine and optimization parameters were studied in die attach process for integrated circuit (IC) packaging. Die attach process is one that is very important IC packaging manufacturing. This process is attaching a die or chip take to leadframe or substrate using die bonding machine.
Don Klaitabtim +3 more
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Journal of Micromechanics and Microengineering, 2020 Among the advanced integrated circuit (IC) integration methods, three-dimensional heterogeneous integration with through-silicon via (TSV) technology showed great potential towards the system-level integration with an increased interconnect density in a smaller footprint. However, the heat mitigation across several dies remains a critical issue in this
Hemanth Kumar Cheemalamarri +3 more
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Ninth IEEE/CHMT International Symposium on Electronic Manufacturing Technology,Competitive Manufacturing for the Next Decade, 2002 The authors present a characterization methodology using per-die test structures to address the need for accurate and reliable product-process models for mixed-signal IC designs. These product-process relationships are critical in generating guardbands and forecasting production yields based on predicted product performance across process variations ...
N. Goel +3 more
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Proceedings of the 5th Electronics Packaging Technology Conference (EPTC 2003), 2004 Delamination at the interface between a silicon backside and the die attach paste has been reported, and this delamination led to package cracking, resulting in reliability problems. In this paper, a series of experiments was conducted to investigate factors affecting the interfacial adhesion between the die back side and the attach paste of an ...
G.H. Lim, E. Low, A.C. Tan
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