Results 241 to 250 of about 135,051 (299)
Some of the next articles are maybe not open access.
Inter-die signaling in three dimensional integrated circuits
2008 IEEE Custom Integrated Circuits Conference, 2008This work discusses a three dimensional network on chip (3D NoC) fabricated in the 0.18 mum MIT Lincoln Laboratories 3D FDSOI 1.5 V process. As a proof of concept, a three tier, 27 node, NoC test chip occupying 4 mm2 per tier was designed and tested.
Christopher Mineo +3 more
openaire +1 more source
Scheduling Integrated Circuit Assembly Operations on Die Bonder
IEEE Transactions on Electronics Packaging Manufacturing, 2007Solving the integrated circuit (IC) assembly scheduling problem (ICASP) is a very challenging task in the IC manufacturing industry. In the IC assembly factories, the jobs are assigned processing priorities and are clustered by their product types, which must be processed on groups of identical parallel machines.
W. L. Pearn, S. H. Chung, C. M. Lai
openaire +1 more source
Detecting a trojan die in 3D stacked integrated circuits
2017 IEEE North Atlantic Test Workshop (NATW), 2017While 3D integrated circuits provide many security advantages, one disadvantage is the insertion of a Trojan die into the stack. In this paper, we explore a technique to detect an extra die through delay analysis.
Soha Alhelaly +5 more
openaire +1 more source
Thermal Effect of TSVs in 3D Die-Stacked Integrated Circuits
2011 14th Euromicro Conference on Digital System Design, 2011Shorter interconnects and higher integration are among the benefits that 3D die-stacking is expected to bring to future integrated circuits. However, when stacking power-dissipating dies one on top of the other, the total power density increases accordingly. As a result, temperatures in 3DICs are exacerbated.
Hadrien A. Clarke, Kazuaki Murakami
openaire +1 more source
2018 19th International Conference of Young Specialists on Micro/Nanotechnologies and Electron Devices (EDM), 2018
This work represents results obtained during research of high frequency IC packaging. The interface between IC die and PCB is described and its inner structure is developed: contact pads on IC die, bondwires and chip outputs. As an example of method developed the interface effects into device development and characteristics are shown for the LNA module
Andrey A. Antonov, Igor K. Surin
openaire +1 more source
This work represents results obtained during research of high frequency IC packaging. The interface between IC die and PCB is described and its inner structure is developed: contact pads on IC die, bondwires and chip outputs. As an example of method developed the interface effects into device development and characteristics are shown for the LNA module
Andrey A. Antonov, Igor K. Surin
openaire +1 more source
Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits
2018 IEEE International Test Conference (ITC), 2018Multi-die stacked ICs are getting increasing traction in the market, fueled by innovations in wafer processing technologies (e.g., vertical inter-die and intra-die connections), stack assembly, and advanced packaging approaches (e.g., wafer-level packaging).
Marinissen, Erik Jan +5 more
openaire +1 more source
A die-on-board PCB for testing high-speed integrated circuits
2015 IEEE Applied Electromagnetics Conference (AEMC), 2015Chip-on-board (COB) printed circuit boards (PCB) appear to be a very attractive solution for testing high-speed integrated circuits (IC). Attaching the bare die directly on a PCB takes away the packaging cost, which is as high as the chip fabrication cost or more when it comes to the high-speed ICs. Wafer probing is a good alternative, but may not come
Mukul Ratwani +3 more
openaire +1 more source
Thermal impact of extreme die thinning in bump-bonded three-dimensional integrated circuits
Microelectronics Reliability, 2017Abstract In three-dimensional integrated circuits (3DICs) aggressive wafer-thinning can lead to large thermal gradients, including spikes in individual device temperatures. In a non-thinned circuit, the large bulk silicon wafer on which devices are built works as a very good thermal conductor, enabling heat to diffuse laterally.
Samson Melamed +5 more
openaire +1 more source
2018 15th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON), 2018
In this paper, installation automatic die bonding machine and optimization parameters were studied in die attach process for integrated circuit (IC) packaging. Die attach process is one that is very important IC packaging manufacturing. This process is attaching a die or chip take to leadframe or substrate using die bonding machine.
Tanatpol Nanthavittayaporn +3 more
openaire +1 more source
In this paper, installation automatic die bonding machine and optimization parameters were studied in die attach process for integrated circuit (IC) packaging. Die attach process is one that is very important IC packaging manufacturing. This process is attaching a die or chip take to leadframe or substrate using die bonding machine.
Tanatpol Nanthavittayaporn +3 more
openaire +1 more source
Never say die [integrated circuit tests]
IEE Review, 2005Perfection is an illusion - even integrated circuits that pass all tests at birth can lose their abilities in old age. New research is looking at ways of stopping so many chips ending up on the scrap heap. The paper looks at whether escalating gate counts on integrated circuits will make the fault-free chip an unrealisable ideal, and what this would ...
openaire +1 more source