Results 261 to 270 of about 135,759 (319)
On-die sensors for measuring process and environmental variations in integrated circuits
Proceedings of the 20th symposium on Great lakes symposium on VLSI, 2010 We present compact on-die variation monitoring circuits for measuring process and environmental fluctuations in product chips. The process characterization structure can be used to isolate process induced systematic and random variation in NFET and PFET devices.
Kanak Agarwal
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CMOS Sensor Arrays for High Resolution Die Stress Mapping in Packaged Integrated Circuits
IEEE Sensors Journal, 2013 This paper reports the design, calibration and application of multiplexed arrays of piezoresistive field-effect transistor stress sensors fabricated in a standard complementary-metal-oxide semiconductor (CMOS) process. Two complementary arrays of 256-current mirror sensor cells provide high spatial density stress mapping with approximately 300 pts/mm2 ...
Yonggang Chen +2 more
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Experimental Measurement of the Thermal Performance of a Two-Die 3D Integrated Circuit (3D IC)
Volume 2: Thermal Management; Data Centers and Energy Efficient Electronic Systems, 2013 Accurate measurement of the thermal performance of vertically-stacked three-dimensional integrated circuits (3D ICs) is critical for optimal design and performance. Experimental measurements also help validate thermal models for predicting the temperature field in a 3D IC. This paper presents results from thermal measurements on a two-die 3D IC.
Leila Choobineh +3 more
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Integrated Circuit Die Level Yield Prediction Using Deep Learning
2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), 2022 Petr Lenhard +2 more
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Applied Thermal Engineering, 2013 Abstract There is much interest in 3D integrated circuits (3D IC) technology for vertical integration of multiple device planes in semiconductor devices. Stacking several device planes vertically offers significant electrical performance improvements. This can also lead to reduced design and manufacturing costs.
Leila Choobineh, Ankur Jain
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Advances in Electronic Packaging, Parts A, B, and C, 2005 This paper presents a method of finite element analysis for calculating moisture concentration in non-isothermal and non-steady states of moisture for integrated circuit packages composed of dissimilar moisture-permeable materials. The method can address non-Fickian behavior of materials in moisture diffusivity.
Hiroyuki Tanaka, Takashi Numata
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18th International Reliability Physics Symposium, 1980 A technique (the capacitance-ratio test) is described for assessing the water content of hermetic packages containing an integrated circuit die. It is based on a theoretical analysis which shows that the frequency dependence of the capacitance between a selected pair of IC metallisation tracks can be used to derive the moisture induced component of ...
R P Merrett, S P Sim, J P Bryant
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Novel technology of III-V die-bonded SOI photonic integrated circuits
Emerging Applications in Silicon Photonics II, 2021In the frame of the H2020 PICTURE project, we designed and developed densely integrated photonic devices and transceiver (TRx) circuits for high bit-rate telecom and datacom applications. We implemented a process with four different InP-based dies bonded on SOI wafers.
Delphine Néel +9 more
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Inter-die signaling in three dimensional integrated circuits
2008 IEEE Custom Integrated Circuits Conference, 2008This work discusses a three dimensional network on chip (3D NoC) fabricated in the 0.18 mum MIT Lincoln Laboratories 3D FDSOI 1.5 V process. As a proof of concept, a three tier, 27 node, NoC test chip occupying 4 mm2 per tier was designed and tested.
Christopher Mineo +3 more
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2018 19th International Conference of Young Specialists on Micro/Nanotechnologies and Electron Devices (EDM), 2018
This work represents results obtained during research of high frequency IC packaging. The interface between IC die and PCB is described and its inner structure is developed: contact pads on IC die, bondwires and chip outputs. As an example of method developed the interface effects into device development and characteristics are shown for the LNA module
Andrey A. Antonov, Igor K. Surin
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This work represents results obtained during research of high frequency IC packaging. The interface between IC die and PCB is described and its inner structure is developed: contact pads on IC die, bondwires and chip outputs. As an example of method developed the interface effects into device development and characteristics are shown for the LNA module
Andrey A. Antonov, Igor K. Surin
openaire +1 more source