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Sensorless vector-controlled induction motor drives: Boosting performance with Adaptive Neuro-Fuzzy Inference System integrated augmented Model Reference Adaptive System. [PDF]

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A Low Jitter Double-Tailed Strong-Arm Latch Based Digital-to-Time Converter (DTC)

2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2020
Digital to time converters (DTCs) have recently become important in phase comparison path in low jitter fractional- $N$ phase-locked loops (PLLs). This paper proposes a simple technique to implement a DTC using the Schmitt trigger. The proposed DTC consists of a double-tailed Strong-Arm latch that acts as a comparator, unlike other DTCs that involve ...
Zeeshan Ali, Makwana Harshit R, Shalabh Gupta   +2 more
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High-resolution pulse generator based on a fully programmable Digital-to-Time Converter (DTC) IP-Core

2018 IEEE Nuclear Science Symposium and Medical Imaging Conference Proceedings (NSS/MIC), 2018
A novel high-performance Digital-to-Time Converter (DTC) organized as an IP-Core (DTC-IP), compatible with 28-nm 7-Series Xilinx Field Programmable Gate Arrays (FPGAs) and System-on-Chips (SoCs) is introduced.The system is suited for generating in parallel multiple digital waveforms that are characterized by programmable pulse width (duty-cycle) and ...
Garzetti, F., Lusardi, N., Lalla, L. Di, Gustin, M., Geraci, A.   +4 more
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A high resolution Time-to-Digital Converter (TDC) based on self-calibrated Digital-to-Time Converter (DTC)

2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), 2017
Based on the parallel DTCs as delay cells, a 4-bit TDC with adjustable 0.7ps∼1.4ps resolution and 11ps∼22ps dynamic range is proposed in this paper. In this design, an extremely high resolution DTC is presented, achieving 15.6fs delay per LSB. By utilizing 16 DTCs which are adjusted to have the same time interval among two neighboring DTCs, a highly ...
Tingbing Ouyang, Bo Wang, Lizhao Gao, Jiangtao Gu, Chao Zhang   +4 more
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A 12-bit digital-to-time converter (DTC) for time-to-digital converter (TDC) and other time domain signal processing applications

NORCHIP 2010, 2010
This paper describes a digital-to-time converter (DTC) architecture that can be used as a fine interpolator in a time-to-digital converter (TDC) or as an adjustable delay in clock deskewing, for example. The new architecture of the DTC achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range.
Salim Al-Ahdab, Antti Mantyniemi, Juha Kostamovaara   +2 more
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A 12-bit digital-to-time converter (DTC) with sub-ps-level resolution using current DAC and differential switch for time-to-digital converter (TDC)

2012 IEEE International Instrumentation and Measurement Technology Conference Proceedings, 2012
This paper describes a digital-to-time converter (DTC) architecture that can be used as interpolator in a time-to-digital converter (TDC). The new architecture of the DTC achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range.
Mäntyniemi Antti, Kostamovaara Juha Tapio, Alahdab Salim   +2 more
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A 2.56-µs Dynamic Range, 31.25-ps Resolution 2-D Vernier Digital-to-Time Converter (DTC) for Cell-Monitoring

2024 IEEE International Symposium on Circuits and Systems (ISCAS)
Capacitive sensor array (CSA) has emerged as a prominent approach in the field of biomedical detection, particularly for the analysis of cell morphology and the construction of a Cell-on-CMOS platform.
Heng-Yu Liu, Lin-Hung Lai, Wen-Yue Lin, Yu-Wei Lu, Yi-Wei Lin, Chen-Yi Lee   +5 more
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Time-Interpolated Vernier Digital-to-Time Converter with Applications in Time-Mode SAR TDC

IEEE International New Circuits and Systems Conference, 2023
This paper proposes an 8 bit time-interpolated Vernier digital-to-time converter (DTC) consisting of a 4-bit Vernier delay line coarse DTC and a 4 bit time interpolator fine DTC with applications in a time-based successive approximation register time-to ...
Daniel Junehee Lee, Fei Yuan, Yushi Zhou
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A Cyclic Vernier Digital-to-Time Converter for Time-Mode Successive Approximation TDC

Midwest Symposium on Circuits and Systems, 2023
This paper presents an 8-bit cyclic Vernier digital-to-time converter (DTC) for time-mode successive approximation register time-to-digital converters (SAR TDCs).
Daniel Junehee Lee, Fei Yuan, Yushi Zhou
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32.2 A 14nm Analog Sampling Fractional-N PLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels

IEEE International Solid-State Circuits Conference, 2021
A local oscillator (LO) for 5G new radio requires sub-100fs rms jitter to support 64-OAM and $2\times2$ MIMO under non-ideal channel conditions [1]. Although fractional-N phase-locked loops (PLLs) employing digital-to-time converters (DTCs) and sampling ...
Wanghua Wu, Chih-Wei Yao, Chengkai Guo, Pei-Yuan Chiang, Pak-Kim Lau, Lei Chen, S. Son, T. Cho   +7 more
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