Results 121 to 130 of about 474 (139)
Heterogeneous Integration Technology Drives the Evolution of Co-Packaged Optics. [PDF]
Micromachines (Basel)Gao H, Yan W, Zhang D, Yu D.
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2018 IEEE Nuclear Science Symposium and Medical Imaging Conference Proceedings (NSS/MIC), 2018 A novel high-performance Digital-to-Time Converter (DTC) organized as an IP-Core (DTC-IP), compatible with 28-nm 7-Series Xilinx Field Programmable Gate Arrays (FPGAs) and System-on-Chips (SoCs) is introduced.The system is suited for generating in parallel multiple digital waveforms that are characterized by programmable pulse width (duty-cycle) and ...
Garzetti, F. +4 more
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A Low Jitter Double-Tailed Strong-Arm Latch Based Digital-to-Time Converter (DTC)
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2020Digital to time converters (DTCs) have recently become important in phase comparison path in low jitter fractional- $N$ phase-locked loops (PLLs). This paper proposes a simple technique to implement a DTC using the Schmitt trigger. The proposed DTC consists of a double-tailed Strong-Arm latch that acts as a comparator, unlike other DTCs that involve ...
Zeeshan Ali 0005 +2 more
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NORCHIP 2010, 2010
This paper describes a digital-to-time converter (DTC) architecture that can be used as a fine interpolator in a time-to-digital converter (TDC) or as an adjustable delay in clock deskewing, for example. The new architecture of the DTC achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range.
Salim Al-Ahdab +2 more
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This paper describes a digital-to-time converter (DTC) architecture that can be used as a fine interpolator in a time-to-digital converter (TDC) or as an adjustable delay in clock deskewing, for example. The new architecture of the DTC achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range.
Salim Al-Ahdab +2 more
openaire +3 more sources
2012 IEEE International Instrumentation and Measurement Technology Conference Proceedings, 2012
This paper describes a digital-to-time converter (DTC) architecture that can be used as interpolator in a time-to-digital converter (TDC). The new architecture of the DTC achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range.
Mäntyniemi Antti +2 more
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This paper describes a digital-to-time converter (DTC) architecture that can be used as interpolator in a time-to-digital converter (TDC). The new architecture of the DTC achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range.
Mäntyniemi Antti +2 more
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2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), 2017
Based on the parallel DTCs as delay cells, a 4-bit TDC with adjustable 0.7ps∼1.4ps resolution and 11ps∼22ps dynamic range is proposed in this paper. In this design, an extremely high resolution DTC is presented, achieving 15.6fs delay per LSB. By utilizing 16 DTCs which are adjusted to have the same time interval among two neighboring DTCs, a highly ...
Tingbing Ouyang +4 more
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Based on the parallel DTCs as delay cells, a 4-bit TDC with adjustable 0.7ps∼1.4ps resolution and 11ps∼22ps dynamic range is proposed in this paper. In this design, an extremely high resolution DTC is presented, achieving 15.6fs delay per LSB. By utilizing 16 DTCs which are adjusted to have the same time interval among two neighboring DTCs, a highly ...
Tingbing Ouyang +4 more
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A High-Linearity Digital-to-Time Converter Technique: Constant-Slope Charging [PDF]
IEEE Journal of Solid-State Circuits, 2015 A digital-to-time converter (DTC) controls time delay by a digital code, which is useful, for example, in a sampling oscilloscope, fractional-N PLL, or time-interleaved ADC.
Claudia Palattella +2 more
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A Sensitive Method to Measure the Integral Nonlinearity of a Digital-to-Time Converter Based on Phase Modulation [PDF]
IEEE Transactions on Circuits and Systems II: Express Briefs, 2015 A digital-to-time converter (DTC) produces a time delay based on a digital code. Similar to data converters, linearity is a key metric for a DTC and it can be characterized by its integral nonlinearity (INL). However, measuring the INL of a subpicosecond-
Claudia Palattella +2 more
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2024 IEEE International Symposium on Circuits and Systems (ISCAS)
Heng-Yu Liu +5 more
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Heng-Yu Liu +5 more
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, 2015 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, 24 - 27 May 2015In this paper, a digital-to-time converter (DTC) assisting a time-to-digital converter (TDC) as a fractional phase error detector in an ultra-low power ...
Yao-Hong Liu +2 more
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