Results 131 to 140 of about 3,174 (179)

A Digital-to-Time Converter Based on Crystal Oscillator Waveform Achieving 86-fs Jitter in 22-nm FD-SOI CMOS

Radio Frequency Integrated Circuits Symposium, 2022
In this paper, we propose a digital-to-time conversion (DTC) technique operating entirely in the sinusiodal waveform voltage domain of a crystal oscillator (XO) before the signal's final slicing into the time-domain of the programmably delayed clock ...
Xi Chen, T. Siriburanon, Zhongzheng Wang, Jianglin Du, Yizhe Hu, Anding Zhu, R. Staszewski   +6 more
semanticscholar   +1 more source

High-Resolution Programmable Delay Line IP-Core based on Digital-to-Time Converter for FPGAs

Nuclear Science Symposium and Medical Imaging Conference, 2022
In this paper, we are going to present a Digital-to-Time Delay-line (DTC-DL) IP-Core, capable of detecting the rising edge of an asynchronous and aperiodic input signal, and replicating it at its output, with a dynamically programmable delay.
N. Corna, F. Garzetti, N. Lusardi, A. Costa, E. Ronconi, M. Cattaneo, A. Geraci   +6 more
semanticscholar   +1 more source

A Digital to Time Converter Assisted TA-TDC with High Resolution for Low Power ADPLL in 22nm CMOS

International Conference on ASIC, 2021
In this paper, a time amplifier (TA) based time-to-digital converter (TDC) as a fractional phase detector with high resolution and low power is presented in 22nm CMOS, which is a key module of an ADPLL for low power BLE application.
Liu Wang, Guojing Ye, Yumei Huang
semanticscholar   +1 more source

A Feedforward and Feedback Constant-Slope Digital-to-Time Converter in 28nm CMOS Achieving ≤ 0.12% INL/Range over >100mV Supply Range

Symposium on VLSI Circuits, 2021
Advanced techniques focusing on ultra-low jitter and spurs in integer-N PLLs, such as subsampling, injection locking and type-I architectures, have been extensively explored in the last decade.
Peng Chen, Feifei Zhang, Suoping Hu, R. Staszewski   +3 more
semanticscholar   +1 more source

A 12bit 100fs Resolution Multi-Stage Digital-to-Time Converter with Dynamic Element Matching

Information and Communication Technologies and Accessibility, 2021
A 12bit 100fs resolution Digital-to-Time Converter (DTC) for frac-N PLL is proposed. To avoid the linearity degradation of a single stage DTC covering a large delay range, the DTC is implemented in a multistage topology, with multiple DTC stages cascaded
Xiongzhong Lin, Gang Zhang
semanticscholar   +1 more source

A high precision, high linearity 10 bit Digital-to-Time Converter circuit

International Conference on Robotics and Control Engineering, 2021
In this paper, a high precision, high linearity 10 bit Digital-to-Time Converter (DTC) circuit was designed and implemented using a conventional open loop amplifier comparator and voltage reference source.
Changpei Qiu, Xin’an Wang, Xing Zhang, Bo Wang, Tianxia Zhao, Qiuping Li   +5 more
semanticscholar   +1 more source

A Low-Noise Digital-to-Time Converter Exploiting Waveform of Integrated Crystal Oscillator

IEEE Journal of Solid-State Circuits
In this article, we propose a digital-to-time conversion technique operating entirely in the sinusoidal waveform voltage domain of a crystal oscillator (XO) before the signal’s final slicing into the time domain of a programmably delayed clock.
T. Siriburanon, Xi Chen, Chunxiao Liu, Jianglin Du, Anding Zhu, R. Bogdan Staszewski   +5 more
semanticscholar   +1 more source

Digital-to-Time Converter and Its Application to Fractional-N Frequency Synthesis: Circuits from a Systems Prospective

IEEE Solid-State Circuits Magazine
This article provides a tutorial on digital-to-time converters (DTC), which are the core blocks of many electronic applications. Common DTC circuit topologies and major DTC timing errors are explained in detail.
Wanghua Wu
semanticscholar   +1 more source

Method to Determine Quantization-Related Parameters of the Digital-to-Time Converter in a Fractional-N Frequency Synthesizer

IEEE Transactions on Circuits and Systems Part 1: Regular Papers
Digital-to-time converters (DTC’s) used in fractional-N frequency synthesizers attempt to cancel the accumulated quantization error (QE) introduced by the divider controller with a view to recovering the integer-N phase noise (PN) performance.
Xu Wang, Michael Peter Kennedy
semanticscholar   +1 more source

A Dual-Alternating-Slope Digital-to-Time Converter Leveraging Mismatch to Improve Delay Step Size

IEEE Journal of Solid-State Circuits
This article introduces a dual-alternating-slope digital-to-time converter (DASDTC) topology that reduces the dependency of DTC delay on component values and power supply.
Nimit Jain, E. Klumperink, H. Rumpt, Bram Nauta   +3 more
semanticscholar   +1 more source