Results 11 to 20 of about 66,202 (261)

Discrete Memristor and Discrete Memristive Systems

Entropy, 2022
In this paper, we investigate the mathematical models of discrete memristors based on Caputo fractional difference and G–L fractional difference. Specifically, the integer-order discrete memristor is a special model of those two cases.
Shaobo He, Donglin Zhan, Huihai Wang, Kehui Sun, Yuexi Peng   +4 more
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Conversion‐less algebraic interleaver architecture for low‐latency IDMA systems

Electronics Letters, 2023
This letter presents a conversion‐less algebraic interleaver architecture for low‐latency interleave division multiple access (IDMA) systems. The existing architectures adopt the two‐step approach that first generates a set of sequential indices, and ...
Byeong Yong Kong
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A Monotonic Early Output Asynchronous Full Adder

Technologies, 2023
This article introduces a novel asynchronous full adder that operates in an input–output mode (IOM), displaying both monotonicity and an early output characteristic.
Padmanabhan Balasubramanian, Douglas L. Maskell   +1 more
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Tunnel Field-Effect Transistor: Impact of the Asymmetric and Symmetric Ambipolarity on Fault and Performance in Digital Circuits

Journal of Low Power Electronics and Applications, 2022
Tunnel Field-Effect Transistors (TFETs) have been considered one of the most promising technologies to complement or replace CMOS for ultra-low-power applications, thanks to their subthreshold slope below the well-known limit of 60 mV/dec at room ...
Chiara Elfi Spano, Fabrizio Mo, Roberta Antonina Claudino, Yuri Ardesi, Massimo Ruo Roch, Gianluca Piccinini, Marco Vacca   +6 more
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High-Speed and Energy-Efficient Carry Look-Ahead Adder

Journal of Low Power Electronics and Applications, 2022
The carry look-ahead adder (CLA) is well known among the family of high-speed adders. However, a conventional CLA is not faster than other high-speed adders such as a conditional sum adder (CSA), a carry-select adder (CSLA), and the Kogge–Stone adder ...
Padmanabhan Balasubramanian, Nikos E. Mastorakis   +1 more
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Evaluating the robustness of multimodal task load estimation models

Frontiers in Computer Science
Numerous studies have focused on constructing multimodal machine learning models for estimating a person's cognitive load. However, a prevalent limitation is that these models are typically evaluated on data from the same scenario they were trained on ...
Andreas Foltyn, Jessica Deuschel, Nadine R. Lang-Richter, Nina Holzer, Maximilian P. Oppelt, Maximilian P. Oppelt   +5 more
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Digital Algebra and Circuits [PDF]

, 2003
Digital numbers D are the world’s most popular data representation: nearly all texts, sounds and images are coded somewhere in time and space by binary sequences. The mathematical construction of the fixed-point D ≃ Z 2 and floating-point D′ ≃ Q 2 digital numbers is a dual to the classical constructions of the real numbers R.
openaire   +1 more source

Higher than 60% Dielectric Tunability in Ba_0.6Sr_0.4TiO₃ Films Using TiO₂ Anatase Buffer Layers

Nanomaterials
In this work, Ba0.6Sr0.4TiO3 (BST) films were deposited on Si(100) and Pt(111)/Ti/SiO2/Si(100) substrates using the pulsed laser deposition (PLD) technique.
Pengzhan Zhang, Jiaming He, Xinyu Liu, Leng Zhang, Ling Zhang, Danbei Wang, Kongpin Wu, Sake Wang   +7 more
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HawkPU: An Efficient and Low-Latency Hardware Architecture for HAWK Signature Generation and Verification

Transactions on Cryptographic Hardware and Embedded Systems
HAWK is the only lattice-based candidate in the second round of additional digital signature schemes of the NIST post-quantum cryptography (PQC) standardization process, which is characterized by its low latency, compact storage requirements, and ...
Rui Wang, Yihong Zhu, Wenping Zhu, Yi Ouyang, Bohan Yang, Hanning Wang, Min Zhu, Chen Chen, Aoyang Zhang, Leibo Liu   +9 more
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A Low-Power JPEG XS Frame Buffer Codec for On-Chip Display Systems

Applied Sciences
Power consumption in portable display systems is significantly affected by the energy cost of frame buffer memory accesses between the graphics processing unit (GPU) and the display processing unit (DPU).
Piotr Chodorowski, Dariusz Kania
doaj   +1 more source