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Digital LDO Based Power Signature Generation Circuit for IoT Security
2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), 2020Power analysis or power fingerprinting has been demonstrated as a potent tool to detect malicious operation or adversary attacks. However, current methods to extract power traces for power analysis typically require bulky and power hungry equipment, which prevents integrating power analysis methods in IoT devices.
David E. Thompson +2 more
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Ratioed Logic Comparator Based Digital LDO Regulator in 22nm FDSOI
2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020This paper presents a fast and an efficient digital LDO (DLDO) regulator utilizing a clock-less ratioed logic comparator (RLC). In addition to eliminating the clock, the proposed RLC-DLDO removes the shift registers used in the conventional DLDO. It achieves a transient speed improvement in the ns range and a quiescent current reduction by 9X over the ...
Dima Kilani +2 more
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A Fully on-Chip Digitally Assisted LDO Regulator With Improved Regulation and Transient Responses
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018This paper proposes a fully-on-chip mixed-mode low-dropout (LDO) regulator with regulation and transient response enhanced. A Miller compensation capacitor and a buffer stage are used to achieve stability and improve power MOS gate slew rate. The ultra-fast voltage buffer helps further improve the load transient recovery speed and reduce the chip area ...
Han Li, Chenchang Zhan, Ning Zhang
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Design of a near-threshold digital LDO with fast transient response
2014 International SoC Design Conference (ISOCC), 2014A near-threshold digital LDO (DLDO) with fast transient response is presented in this paper. In order to improve settling time, a voltage-controlled delay line (VCDL) with a new proposed delay cell is developed to enhance conversion gain. In addition, Vernier-delay-line-based time-to-digital convertor (TDC) is used to quantize phase from phase ...
null Yunsheng Chan, null Yingchieh Ho
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A fully-synthesizable 0.6V digital LDO with dual-loop control using digital standard cells
2016 14th IEEE International New Circuits and Systems Conference (NEWCAS), 2016A fully synthesizable digital low drop-out regulator (LDO) with dual (coarse/fine) loops control is proposed. This structure employs a synchronized comparator to compare the feedback voltage (Vfb) and the desired reference voltage (Vref). A coarse loop is used to simplify the control logic circuit and increase the LDO response speed during the output ...
Jun Liu 0038, Nima Maghari
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A Dual-Loop Digital LDO Regulator with Asynchronous-Flash Binary Coarse Tuning
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018This paper presents a dual-loop digital low-dropout regulator (DLDO) with asynchronous-flash (AF) binary coarse tuning for fast transient response. In steady state, the DLDO operates with a unary-weighted low power fine-tune loop to improve the regulation accuracy.
Yuanqing Huang +3 more
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Asynchronous Domino Binary search Digital LDO
2021 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2021Wei-Bin Yang +3 more
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Review, Survey, and Benchmark of Recent Digital LDO Voltage Regulators
2022 IEEE Custom Integrated Circuits Conference (CICC), 2022Zhaoqing Wang +3 more
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A Digital LDO Regulator With a Self-Clocking Burst Logic for Ultralow Power Applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019Conventional capless digital low-dropout (DLDO) regulators adopt either a high-speed clock or the burst mode at the expense of a larger quiescent current in order to overcome the degradation of the load transient response caused by the absence of an external capacitor, which causes high power consumption.
Seong-Jin Yun +3 more
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A Transient-Enhanced Digital-LDO With Adaptive Clock-Edge Control
2023 IEEE 15th International Conference on ASIC (ASICON), 2023Guoqiang Song +3 more
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