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Advanced digital phase-locked loops
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013Analog PLLs do not scale down as process and are not amenable to noise-cancellation and other calibration algorithms; Digital PLLs exploit CMOS scaling and allow for simple, accurate implementation of digiphase and two-point modulation; Typically, DPLLs require TDCs with tight resolution to achieve low phase noise and fractional-spur level, which ...
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2015
One of the most challenging tasks in analog circuit design is to adapt a functional block to ever-new CMOS process technologies. For digital circuits, the number of gates per square milimeter approximately doubles per chip generation. Integration of analog parts in recent deep submicron technologies is much more difficult and additionally complicated ...
Basab Bijoy Purkayastha +1 more
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One of the most challenging tasks in analog circuit design is to adapt a functional block to ever-new CMOS process technologies. For digital circuits, the number of gates per square milimeter approximately doubles per chip generation. Integration of analog parts in recent deep submicron technologies is much more difficult and additionally complicated ...
Basab Bijoy Purkayastha +1 more
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IETE Journal of Education, 2011
AbstractThe paper describes the phase locked loop (PLL) in detail. Emphasis is on Digital Phase Locked loops (DPLL) and All-Digital Phase Locked Loops (ADPLL). Important parameters of the PLLs are described. Different sub-blocks of DPLL and ADPLL are described and discussed in detail. An example design of ADPLL is also discussed.
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AbstractThe paper describes the phase locked loop (PLL) in detail. Emphasis is on Digital Phase Locked loops (DPLL) and All-Digital Phase Locked Loops (ADPLL). Important parameters of the PLLs are described. Different sub-blocks of DPLL and ADPLL are described and discussed in detail. An example design of ADPLL is also discussed.
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2022
This thesis was scanned from the print manuscript for digital preservation and is copyright the author. Researchers can access this thesis by asking their local university, institution or public library to make a request on their behalf. Monash staff and postgraduate students can use the link in the References field.
openaire +1 more source
This thesis was scanned from the print manuscript for digital preservation and is copyright the author. Researchers can access this thesis by asking their local university, institution or public library to make a request on their behalf. Monash staff and postgraduate students can use the link in the References field.
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IEEE Transactions on Circuits and Systems Part 2: Express Briefs, 2007
Kartikeya Mayaram +2 more
exaly
Kartikeya Mayaram +2 more
exaly
Sampling and Quantizing Noise Minimization of a Digital Phase Locked Loop
Proceedings of the IEEE, 1978S K Ray, B N Biswas, A K Bhattacharya
exaly