Results 1 to 10 of about 535 (152)

FPGA Implementation of ADPLL with Ripple Reduction Techniques [PDF]

International Journal of VLSI Design & Communication Systems, 2012
In this paper FPGA implementation of ADPLL using Verilog is presented. ADPLL with ripple reduction techniques is also simulated and implemented on FPGA. For simulation ISE Xilinx 10.1 CAD is used.Vertex5 FPGA (Field Programmable Gate Array) is used for implementation.
Manoj Kumar, Kusum Lata
openaire   +2 more sources

SEC中的全数字锁相环的分析及设计

Guangtongxin yanjiu, 2006
文章首先介绍了全数字锁相环（ADPLL）的基本结构和工作原理,并进行了数学建模,计算了其主要的参数指标;然后,针对SDH设备时钟（SEC）设计了一种切实可行的低抖动ADPLL的电路结构,并对其各个组成部分进行了具体的电路分析和设计,通过微机适当配置,可以使该设计的结果得到优化;最后,通过现场可编程门阵列（FPGA）验证,给出了测试结果。
张继勇, 王爱国
doaj  

Research on ADPLL for High-Precision Phase Measurement

Symmetry
The inter-satellite laser interferometer, which functions as a high-performance displacement sensor, will be used in forthcoming space-based gravitational wave detection missions. The readout of these interferometers is typically performed by phasemeters based on all-digital phase-locked loops (ADPLLs) implemented in FPGAs.
Weilai Yao, Chenying Sun, Xindong Liang, Jianjun Jia   +3 more
openaire   +1 more source

Digital Phase-Locked Loops: Exploring Different Boundaries

IEEE Open Journal of the Solid-State Circuits Society
This article examines the research area of digital phase-locked loops (DPLLs), a critical component in modern electronic systems, from wireless communication devices to RADAR systems and digital processors. As the demands for higher integration levels in
Yuncheng Zhang, Dingxin Xu, Kenichi Okada   +2 more
doaj   +1 more source

Exploring the Landscape of Phase-Locked Loop Architectures: A Comprehensive Review

IEEE Access
This paper aims to explore diverse landscape of Phase Locked Loops (PLLs), offering a comprehensive categorization and in-depth analysis of their underlying working principles.
Debojyoti Dutta, Sai Pranshu Tumukunta, N. R. Sivaraaj, K. K. Abdul Majeed   +3 more
doaj   +1 more source

Nonlinearity-Induced Spur Analysis in Fractional-N Synthesizers With ΔΣ Quantization Cancellation

IEEE Open Journal of the Solid-State Circuits Society
A fractional-N frequency synthesizer with low total jitter [e.g., <50fsrms, accounting for both phase noise (PN) and spurs] is essential for enabling the emerging 5G/6G and other high-speed wireless communication standards (e.g., WiFi-6/7).
Yizhe Hu, Weichen Tao, Robert Bogdan Staszewski   +2 more
doaj   +1 more source

Linearity Calibration Method for Stochastic Time-to-Digital Converters

IEEE Access
Stochastic Time-to-Digital Converters (STDCs) can theoretically achieve very fine time resolutions utilizing random time offsets caused by device mismatch rather than relying on delay elements.
Woongdae Na, Hayun Chung
doaj   +1 more source

Digitally Controlled Oscillator with High Timing Resolution and Low Complexity for Clock Generation. [PDF]

Sensors (Basel), 2021
Sheng D, Chen WY, Huang HT, Tai L.
europepmc   +1 more source

Chip Design of an All-Digital Frequency Synthesizer with Reference Spur Reduction Technique for Radar Sensing. [PDF]

Sensors (Basel), 2022
Lai WC.
europepmc   +1 more source

Resonant frequency tracking mode on eddy current pulsed thermography non-destructive testing. [PDF]

Philos Trans A Math Phys Eng Sci, 2020
Miao L, Gao B, Li H, Tian G.
europepmc   +1 more source