Results 1 to 10 of about 772 (186)
62.5 ps LSB resolution multiphase clock Time to Digital Converter (TDC) implemented on FPGA [PDF]
Journal of King Saud University: Engineering Sciences, 2022 A 13-bit Time to Digital Converter is implemented using multiphase clock technique. Xilinx’s Virtex 5 FPGA platform is used to realize the TDC architecture.
Mahantesh Mattada, Hansraj Guhilot
doaj +5 more sources
High-resolution time-to-digital converters (TDCs) with a bidirectional encoder [PDF]
SSRN Electronic Journal, 2022 A high-resolution time-to-digital converter (TDC) based on wave union (four-edge WU A), dual-sampling, and sub-TDL methods is proposed and implemented in a 16-nm Xilinx UltraScale+ field-programmable gate array (FPGA). We combine WU and dual-sampling techniques to achieve a high resolution.
Yu Wang +3 more
+8 more sources
IEEE Journal of Solid-State Circuits, 2009 This paper describes a time-to-digital converter (TDC) with ~1.2 ps resolution and ~327 mus dynamic range suitable for laser range-finding application for example. The resolution of ~1.2 ps is achieved with interpolation based on a cyclic time domain successive approximation (CTDSA) method that resolves the time difference between two non-repetitive ...
A. Mantyniemi +2 more
exaly +4 more sources
Mutually Coupled Time-to-Digital Converters (TDCs) for Direct Time-of-Flight (dTOF) Image Sensors ‡ [PDF]
Sensors, 2018 Direct time-of-flight (dTOF) image sensors require accurate and robust timing references for precise depth calculation. On-chip timing references are well-known and understood, but for imaging systems where several thousands of pixels require seamless references, area and power consumption limit the use of more traditional synthesizers, such as phase ...
Augusto R. Ximenes +2 more
openalex +8 more sources
PLI-TDC: Super Fine Delay-Time Based Physical-Layer Identification with Time-to-Digital Converter for In-Vehicle Networks [PDF]
Proceedings of the 2021 ACM Asia Conference on Computer and Communications Security, 2021 Recently, cyberattacks on Controller Area Network (CAN) which is one of the automotive networks are becoming a severe problem. CAN is a protocol for communicating among Electronic Control Units (ECUs) and it is a de-facto standard of automotive networks.
Shuji Ohira +3 more
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Firmware-only implementation of time-to-digital converter (TDC) in field-programmable gate array (FPGA) [PDF]
2003 IEEE Nuclear Science Symposium. Conference Record (IEEE Cat. No.03CH37515), 2003 A Time-to-Digital Converter (TDC) implemented in general purpose field-programmable gate array, (FPGA) for the Fermilab CKM experiment will be presented. The TDC uses a delay chain and register array structure to produce lower bits in addition to higher bits from a clock counter.
Jinyuan Wu, Zonghan Shi, I-Chen Wang
openalex +3 more sources
Time--to--Digital Converter (TDC)--Based Resonant Compute--in--Memory for INT8 CNNs with Layer--Optimized SRAM Mapping [PDF]
In recent years, Compute-in-memory (CiM) architectures have emerged as a promising solution for deep neural network (NN) accelerators. Multiply-accumulate~(MAC) is considered a {\textit de facto} unit operation in NNs. By leveraging the inherent parallel processing capabilities of CiM, NNs that require numerous MAC operations can be executed more ...
Dhandeep Challagundla +2 more
+7 more sources
A Size, Weight, Power, and Cost-Efficient 32-Channel Time to Digital Converter Using a Novel Wave Union Method [PDF]
Sensors, 2023 We present a Tapped Delay Line (TDL)-based Time to Digital Converter (TDC) using Wave Union type A (WU-A) architecture for applications that require high-precision time interval measurements with low size, weight, power, and cost (SWaP-C) requirements ...
Saleh M. Alshahry +3 more
doaj +2 more sources
Design and Experiment of Ultrasonic Anemometer Using TDC-GP2 Time-to-Digital Converter
Key Engineering Materials, 2014 An ultrasonic anemometer using TDC-GP2 high-accuracy time measuring chip is studied in this paper, the design of software and hardware parts and principle of flying time measurement using TDC-GP2 chip are also discussed in detail. Under this scheme, a prototype has been fabricated, with simpler circuit architecture.
Han Yu Du, Ming Qin
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A 128-channel Time-to-Digital Converter (TDC) inside a Virtex-5 FPGA on the GANDALF module [PDF]
Journal of Instrumentation, 2012 The GANDALF 6U-VME64x/VXS module has been developed for the digitization and real time analysis of detector signals. To perform different applications such as analog-to-digital or time-to-digital conversions, coincidence matrix formation, fast pattern recognition and trigger generation, this module comes with exchangeable analog and digital mezzanine ...
M. Büchele +6 more
openalex +3 more sources