Results 41 to 50 of about 1,742 (210)
Time-Mode Signal Quantization for Use in Sigma-Delta Modulators [PDF]
The rapid scaling in modern CMOS technology has motivated the researchers to design new analog-to-digital converter (ADC) architectures that can properly work in lower supply voltage.
Mohsen Tamaddon, Mohammad Yavari
doaj +1 more source
Widening and narrowing of time interval due to single‐event transients in 45 nm vernier‐type TDC
Single‐event transients (SETs) due to heavy‐ion (HI) strikes adversely affect the electronic circuits in sub‐100 nm regime in radiation environment.
Pasupathy K. Ramaniharan, Bindu Boby
doaj +1 more source
A 100–750 MS/s 11-Bit Time-to-Digital Converter With Cyclic-Coupled Ring Oscillator
This paper presents the first measured cyclic-coupled ring oscillator (CCRO) time-to-digital converter (TDC). The CCRO realizes a robust true time-domain delay interpolation with sub-gate-delay resolution.
Okko Jarvinen +7 more
doaj +1 more source
A novel time to digital converter architecture for time of flight positron emission tomography
Positron emission tomography (PET) is a molecular imaging technique that provides images of physiological processes inside the body. In clinical applications, PET image quality benefits from the time of flight (TOF) feature.
Luca Fanucci +11 more
core +1 more source
This paper describes FPGA implementation of a high-order continuous-time multi-stage noise-shaping (MASH) $\Delta \Sigma $ time-to-digital converter (TDC).
Ahmad Mouri Zadeh Khaki +4 more
doaj +1 more source
CMOS single photon sensor with in-pixel TDC for Time-of-Flight applications
A CMOS imager that combines single photon sensitivity with photon timing capabilities has been developed for Time-Of-Flight (TOF) measurements and for Time-Correlated Single-Photon Counting (TCSPC) applications.
LUSSANA, RUDI +15 more
core +1 more source
We describe the architecture of a time-to-digital converter (TDC), specially intended to measure the delay resolution of a programmable delay line (PDL).
Chao Chen +4 more
doaj +1 more source
TDC with 1.5% DNL based on a single-stage vernier delay-loop fine interpolation
We present a compact TDC Module based on the Time-to-Digital Converter ASIC fabricated in 0.35 μm CMOS technology. This chip measures the time-interval between two inputs, called START and STOP, with a 10 ps resolution when using a 10 ns reference clock.
MARKOVIC, BOJAN +9 more
core +1 more source
Implementation and development of a DAQ system DELILA at ELI-NP [PDF]
This paper reports the current status of the Data AcQuisition (DAQ) system in ELI-NP, Romania. The DAQ system uses several data-taking electronics modules, CAEN 1730 1725 and 1740 digitizer series, and Mesytec Analog-to-Digital Converter (ADC) and Time ...
Aogaki Sohichiroh, Niculae Stefan
doaj +1 more source
Achievement of Transition Metal Chalcogenides/Oxides in Hydrogen Production by Seawater Electrolysis
Transition metal chalcogenides (TMCs)/oxides have shown great application potential in seawater splitting for hydrogen generation due to their adjustable electronic properties, abundant active sites, and excellent catalytic performance. ABSTRACT Under the impetus of global “dual carbon” goals, green hydrogen has become a key component of the future ...
Xiaohui Du, Xinyu Li, Jianna Li, Tao Sun
wiley +1 more source

