HEART RATE COMPUTATION IMPLEMENTED ON FIELD PROGRAMMABLE GATE ARRAY BOARD
Techne, 2010 Heart rate is the most basic information of heart activities. This paper aims to describe a possible real time system to detect electrocardiogram (ECG) signal, count the R-R interval of the ECG signal, and compute the heart rate.
Ivanna K. Timotius
doaj
Secure Protocol and IP Core for Configuration of Networking Hardware IPs in the Smart Grid
Energies, 2018 Nowadays, the incorporation and constant evolution of communication networks in the electricity sector have given rise to the so-called Smart Grid, which is why it is necessary to have devices that are capable of managing new communication protocols ...
Marcelo Urbina +5 more
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A RESEARCH ON SEAMLESS PLATFORM CHANGE OF REACTOR PROTECTION SYSTEM FROM PLC TO FPGA
Nuclear Engineering and Technology, 2013 The PLC (Programmable Logic Controller) has been widely used to implement real-time controllers in nuclear RPSs (Reactor Protection Systems). Increasing complexity and maintenance cost, however, are now demanding more powerful and cost-effective ...
JUNBEOM YOO, JONG-HOON LEE, JANG-SOO LEE
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A survey of field programmable gate array (FPGA)-based graph convolutional neural network accelerators: challenges and opportunities. [PDF]
PeerJ Comput Sci, 2022 Li S, Tao Y, Tang E, Xie T, Chen R.
europepmc +1 more source
Velocity Signal Measurement Based on FPGA
机车电传动, 2016 In order to reduce CPU resource occupancy rate and the software complexity for velocity measuring, a FPGA(Field Programmable Gate Array) technology to measure velocity and related information was adopted as a supplement of CPU.
LI Hui, LUO Zhengyu, XU Juan
doaj
A FPGA-Based Neuromorphic Locomotion System for Multi-Legged Robots
IEEE Access, 2017 The paper develops a neuromorphic system on a Spartan 6 field programmable gate array (FPGA) board to generate locomotion patterns (gaits) for three different legged robots (biped, quadruped, and hexapod).
Erick Israel Guerra-Hernandez +5 more
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Enhanced Efficiency 3D Convolution Based on Optimal FPGA Accelerator
IEEE Access, 2017 This paper presents an enhanced efficiency 3-D convolution operator based on optimal field programmable gate array (FPGA) accelerator platform. The proposed system takes advantages of the intermediate data delay lines, implemented in an FPGA, to avoid ...
Hai Wang +3 more
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Design and Implementation of JPEG 2000 Image Compression using FPGA
Journal of Engineering and Sustainable Development, 2006 This paper investigates the use of a Field Programmable Gate Array (FPGA Xilinx Virtex-II) to perform hardware implementation for low speed part of JPEG2000 to achieve a real time JPEG2000 system.
Munther N. B. Al-Tikriti +2 more
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High-speed broadband data acquisition system based on FPGA
Journal of Measurement Science and Instrumentation, 2013 A field-programmable gate array（FPGA）based high-speed broadband data acquisition system is designed.The system has a dual channel simultaneous acquisition function.The maximum sampling rate is 500 MSa/s and bandwidth is200 MHz,which solves the large ...
LIU Jun-zhi
doaj
Rapid Prototyping of Field Programmable Gate Array-Based Discrete Cosine Transform Approximations
EURASIP Journal on Advances in Signal Processing, 2003 A method for the rapid design of field programmable gate array (FPGA)-based discrete cosine transform (DCT) approximations is presented that can be used to control the coding gain, mean square error (MSE), quantization noise, hardware cost, and power ...
Trevor W. Fox, Laurence E. Turner
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