Results 1 to 10 of about 47,559 (229)
A General and Efficient Framework for the Rapid Design of Miniaturized, Wideband, and High‐Bit RIS
A general and efficient framework is proposed for the rapid design of high‐performance reconfigurable intelligent surfaces (RISs). This framework integrates advanced antenna design techniques and incorporates various load types, quantities, and values to achieve the design of high‐performance RISs.
Jun Wei Zhang +14 more
wiley +1 more source
Realization of Three-level SVPWM Algorithm Based on FPGA
According to the performance of AC-driving digital control system greatly depends on the process speed of controller, field programmable gate array(FPGA) was introduced to reduce the control period. Three-levels space vector pulse width modulation(SVPWM)
LIN Xin, KOU Shuren, YANG Fan
doaj
Implementación del algoritmo Threefish-256 en hardware reconfigurable
This article presents both the description and results of the Threefish cryptographic algorithm hardware implementation for encryption process.
Nathaly Nieto-Ramírez +1 more
doaj +1 more source
Kecerdasan matematik-logik dalam kalangan pelajar sarjana Pendidikan Teknik dan Vokasional UTHM [PDF]
Kecerdasan matematik-logik sering dikaitkan dengan penguasaan pelajar dalam subjek matematik. Pencapaian pelajar, khususnya pelajar Sarjana Pendidikan Teknik dan Vokasional, Universiti Tun Hussein Onn Malaysia (UTHM) dalam kursus Statistik dalam ...
Mohd Zain, Noorhafiezah
core +1 more source
Terahertz Channel Modeling, Estimation and Localization in RIS‐Assisted Systems
Reconfigurable intelligent surfaces have become a recent intensive research focus. Based on practical applications, channel strategies for RIS‐assisted terahertz wireless communication systems are categorized into three different types: channel modeling, channel estimation, and channel localization.
Hongjing Wang +9 more
wiley +1 more source
Advanced memory optimization techniques are reviewed to enhance the performance of Convolutional Neural Networks (CNNs) and Spiking Neural Networks (SNNs) on hardware accelerators, addressing the real-world challenges in medical imaging.
N. Srikanth Prasad, S. Sundar
doaj +1 more source
Dynamic reconfiguration technologies based on FPGA in software defined radio system [PDF]
Partial Reconfiguration (PR) is a method for Field Programmable Gate Array (FPGA) designs which allows multiple applications to time-share a portion of an FPGA while the rest of the device continues to operate unaffected.
Ke He +3 more
core +2 more sources
Experimental 3D Asynchronous Field Programmable Gate Array (FPGA) [PDF]
Abstract : 3D technology has the potential to significantly enhance the capabilities of a computing platform through tight integration of multiple levels of logic through low-cost vertical interconnects. The goal of this effort is to evaluate the potential of 3D technology in the context of an asynchronous Field Programmable Gate Array developed for ...
openaire +1 more source
Ising machines are emerging as specialized hardware solvers for computationally hard optimization problems. This review examines five major platforms—digital CMOS, analog CMOS, emerging devices, coherent optics, and quantum systems—highlighting physics‐rooted advantages and shared bottlenecks in scalability and connectivity.
Hyunjun Lee, Joon Pyo Kim, Sanghyeon Kim
wiley +1 more source
Implementation of a Recursive Data of Adaptive QRD-RIS Algorithm Using HDI Coder
Matrix inversion is a common function found in many algorithms used in wireless communication systems. As Field Programmable Gate Array (FPGA) become an increasingly attractive platform for wireless communication, it is important to understand the ...
Ali Khalid Jassim +2 more
doaj

