Results 21 to 30 of about 15,482 (245)

FPGA-based accelerator method for Edge Computing [PDF]

Edge computing helps radio-supported mobile systems to process computing tasks on the side ofservers. The proximity to an edge computing node avoids excessive latencies, which benefits the calculation ofreal-time algorithms. Special computing needs arise
Schulz, Peter, Sleahtitchi, Grigore
core   +1 more source

High Level Implementation Methodologies of DSP Module using FPGA and System Generator [PDF]

Engineering and Technology Journal, 2016
This paper presents the high level implementation methodologies of Digital Signal Processing (DSP) module by using the Field Programmable Gate Array (FPGA) andintegrated software environments (ISE) with the System Generator programs.
Majid S. Naghmash, Mousa K. Wali, Amar A. Abdulmajeed   +2 more
doaj   +1 more source

Implemetasi Komputasi Akar Kuadrat Resolusi Tinggi pada Field Programmable Gate Array (FPGA)

Jurnal Teknologi Informasi dan Ilmu Komputer, 2022
Komputasi akar kuadrat diperlukan pada beberapa proses pengendalian, diantaranya untuk Direct Torque Control (DTC) pada sistem penggerak motor yang membutuhkan proses perhitungan yang sangat cepat.
Muhammad Irfan, Hendra Setiawan
doaj   +1 more source

Bias‐Field Free Single‐Frequency CW‐ODMR of Nitrogen‐Vacancy Centers in Diamond for the Detection of Transient Electrical Signals

Advanced Materials Interfaces, EarlyView.
Simplified quantum sensing technique for the detection of short electrical signals occurring in neuronal signaling or bioinspired technologies. We demonstrate a single frequency continuous‐wave optically detected magnetic resonance (CW‐ODMR) approach to sense signals that can be as short as 0.2 ms.
João Paulo Silva, Orlando D. Cunha, Pedro Magalhães, Filipe Camarneiro, Jana B. Nieder   +4 more
wiley   +1 more source

Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs

, 2008
The Field Programmable Counter Array (FPCA) was introduced to improve FPGA performance for arithmetic circuits. An FPCA is a reconfigurable IP core that can be integrated into an FPGA.
Philip Brisk, Frank K. Gurkaynak, Ajay K. Verma, Yusuf Leblebici, Alessandro Cevrero, Verma, Ajay K., Cevrero, Alessandro, Athanasopoulos, Panagiotis, Leblebici, Yusuf, Paolo Ienne, Brisk, Philip, Ienne, Paolo, Parandeh-Afshar, Hadi, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Gurkaynak, Frank K.   +15 more
core   +1 more source

Parallelized Particle Swarm Optimization on FPGA for Realtime Ballistic Target Tracking

Sensors, 2023
This paper addresses the problem of tracking a high-speed ballistic target in real time. Particle swarm optimization (PSO) can be a solution to overcome the motion of the ballistic target and the nonlinearity of the measurement model. However, in general,
Juhyeon Park, Heoncheol Lee, Hyuck-Hoon Kwon, Yeji Hwang, Wonseok Choi   +4 more
doaj   +1 more source

Dataflow computation with intelligent memories emulated on field-programmable gate arrays (FPGAs) [PDF]

Microprocessors and Microsystems, 2002
Abstract This paper presents a new design that implements the data-driven (i.e. dataflow) computation paradigm with intelligent memories. Also, a relevant prototype that employs FPGAs is presented for the support of intelligent memory structures. Instead of giving the CPU the privileged right to decide what instructions to fetch in each cycle (as is ...
Segreen Ingersoll, Sotirios G. Ziavras
openaire   +1 more source

Biodegradable Wireless Soil Urea Sensor Using Metamaterial Perfect Absorber for Distributed Deployment in Precision Agriculture

Advanced Materials Technologies, EarlyView.
In this study, we propose a biodegradable wireless soil urea sensor for precision agriculture. The sensor's electromagnetic response varies depending on the urea concentration, allowing the measurement of relative soil urea concentrations by analyzing the time‐transient electromagnetic response.
Yu Tanaami, Ken Sakabe, Tetsuya Yarimizo, Yasutaka Murakami, Tetsuo Kan, Hiroaki Onoe   +5 more
wiley   +1 more source

Data Packet Processing Acceleration Architecture for Virtual Network Function Based on FPGA [PDF]

Jisuanji gongcheng, 2018
In order to improve the packet processing performance of Virtual Network Function(VNF),this paper comes up with a Field Programmable Gate Array(FPGA)-based General Hardware Accelerator(GHA) architecture.The GHA architecture implements the packet ...
FAN Hongwei,HU Yuxiang,LAN Julong
doaj   +1 more source

An On‐Demand Neuromorphic Vision System Enabled by a Multi‐Paradigm Neuromorphic Device and Hierarchical Reconfigurability Designed from Device to System Level

Advanced Science, EarlyView.
An on‐demand ultra‐reconfigurable intelligent vision system with hierarchical reconfigurability from device to system levels is demonstrated. Through co‐design of a multi‐paradigm device, reconfigurable circuits, and adaptive system architecture/algorithms, the system enables seamless switching among spiking, non‐spiking, neuromorphic imaging (NI), and
Biyi Jiang, Jiayi Xu, Liang Ran, Xinhe Feng, Khalil Harrabi, Yida Li, Longyang Lin, Feichi Zhou   +7 more
wiley   +1 more source