Results 31 to 40 of about 47,559 (229)

Scalability of spin FPGA: A Reconfigurable Architecture based on spin MOSFET

, 2011
Scalability of Field Programmable Gate Array (FPGA) using spin MOSFET (spin FPGA) with magnetocurrent (MC) ratio in the range of 100% to 1000% is discussed for the first time. Area and speed of million-gate spin FPGA are numerically benchmarked with CMOS
Gao Y., Hideyuki Sugiyama, Inokuchi T., Kazutaka Ikegami, Marukame T., Mizue Ishikawa, Nagamine Y., Sugiyama H., Takao Marukame, Tetsufumi Tanamoto, Tomoaki Inokuchi, Yoshiaki Saito   +11 more
core   +1 more source

The use of field-programmable gate arrays for the hardware acceleration of design automation tasks [PDF]

, 1996
This paper investigates the possibility of using Field-Programmable Gate Arrays (Fr’GAS) as reconfigurable co-processors for workstations to produce moderate speedups for most tasks in the design process, resulting in a worthwhile overall design ...
Allinson, Nigel M., Howard, Neil J., Tyrrell, Andrew M.   +2 more
core   +2 more sources

Statistical lossless compression of space imagery and general data in a reconfigurable architecture [PDF]

, 2008
This paper investigates an universal algorithm and hardware architecture for context-based statistical lossless compression of multiple types of data using FPGA (Field Programmable Gate Array) devices which support partial and dynamic reconfiguration ...
Canagarajah, CN, Chen, X, Nunez-Yanez, JL, Vitulli, R   +3 more
core   +2 more sources

A Self-Timed Multipurpose Delay Sensor for Field Programmable Gate Arrays (FPGAs) [PDF]

Sensors, 2013
This paper presents a novel self-timed multi-purpose sensor especially conceived for Field Programmable Gate Arrays (FPGAs). The aim of the sensor is to measure performance variations during the life-cycle of the device, such as process variability, critical path timing and temperature variations.
Gomez Osuna, Carlos, Ituero Herrero, Pablo, López Vallejo, Marisa   +2 more
openaire   +4 more sources

Josephson Junction Model: FPGA Implementation and Chaos-Based Encryption of sEMG Signal through Image Encryption Technique

Complexity, 2022
The field programmable gate array (FPGA) implementation of the nonlinear resistor-capacitor-inductor shunted Josephson junction (NRCISJJ) model and its application to sEMG (Surface ElectroMyoGraphic) signal encryption through image encrypted technique ...
Colince Welba, Dhanagopal Ramachandran, Alexendre Noura, Victor Kamdoum Tamba, Sifeu Takougang Kingni, Pascal Eloundou Ntsama, Pierre Ele   +6 more
doaj   +1 more source

Implemetasi Komputasi Akar Kuadrat Resolusi Tinggi pada Field Programmable Gate Array (FPGA)

Jurnal Teknologi Informasi dan Ilmu Komputer, 2022
Komputasi akar kuadrat diperlukan pada beberapa proses pengendalian, diantaranya untuk Direct Torque Control (DTC) pada sistem penggerak motor yang membutuhkan proses perhitungan yang sangat cepat.
Muhammad Irfan, Hendra Setiawan
doaj   +1 more source

Sequential Discrete Kalman Filter for Real-Time State Estimation in Power Distribution Systems: Theory and Implementation

, 2017
This paper demonstrates the feasibility of implementing Real-Time State Estimators (RTSEs) for Active Distribution Networks (ADNs) in Field-Programmable Gate Arrays (FPGAs) by presenting an operational prototype.
Kettner, Andreas Martin, Paolone, Mario
core   +1 more source

Evaluation of Single-Chip, Real-Time Tomographic Data Processing on FPGA - SoC Devices [PDF]

, 2018
A novel approach to tomographic data processing has been developed and evaluated using the Jagiellonian PET (J-PET) scanner as an example. We propose a system in which there is no need for powerful, local to the scanner processing facility, capable to ...
Białas, P., Curceanu, C., Czerwiński, E., Dulski, K., Flak, B., Gajos, A., Gorgol, M., Głowacz, B., Hiesmayr, B. C., Jasińska, B., Kacprzak, K., Kajetanowicz, M., Kisielewska, D., Korcyl, G., Kowalski, P., Kozik, T., Krawczyk, N., Krzemień, W., Kubicz, E., Mohammed, M., Moskal, P., Niedźwiecki, Sz., Pawlik-Niedźwiecka, M., Pałka, M., Raczyński, L., Rajda, P., Rudy, Z., Salabura, P., Sharma, N. G., Sharma, S., Shopa, R. Y., Silarski, M., Skurzok, M., Strzempek, P., Wieczorek, A., Wiślicki, W., Zaleski, R., Zgardzińska, B., Zieliński, M.   +38 more
core   +2 more sources

Parallelized Particle Swarm Optimization on FPGA for Realtime Ballistic Target Tracking

Sensors, 2023
This paper addresses the problem of tracking a high-speed ballistic target in real time. Particle swarm optimization (PSO) can be a solution to overcome the motion of the ballistic target and the nonlinearity of the measurement model. However, in general,
Juhyeon Park, Heoncheol Lee, Hyuck-Hoon Kwon, Yeji Hwang, Wonseok Choi   +4 more
doaj   +1 more source

High Level Implementation Methodologies of DSP Module using FPGA and System Generator [PDF]

Engineering and Technology Journal, 2016
This paper presents the high level implementation methodologies of Digital Signal Processing (DSP) module by using the Field Programmable Gate Array (FPGA) andintegrated software environments (ISE) with the System Generator programs.
Majid S. Naghmash, Mousa K. Wali, Amar A. Abdulmajeed   +2 more
doaj   +1 more source