Results 51 to 60 of about 8,077,861 (214)

Neuromorphic Near‐Sensor and In‐Sensor Computing Enabled by Next‐Generation Material‐Based Sensors

Advanced Science, EarlyView.
This Review presents a structural framework that classifies neuromorphic sensing into near‐sensor and in‐sensor architectures, clarifying physical coupling between sensing and computation. The framework connects neural and synaptic device functions with recent advances in optical, mechanical, and chemical sensing, compares energy consumption and ...
Su Yeon Jung, Gwang Ya Kim, Sejin Kim, Hyunjong Seo, Se Gi Lee, Sang Min Won, Dongjoon Rhee, Joohoon Kang   +7 more
wiley   +1 more source

Data Packet Processing Acceleration Architecture for Virtual Network Function Based on FPGA [PDF]

Jisuanji gongcheng, 2018
In order to improve the packet processing performance of Virtual Network Function(VNF),this paper comes up with a Field Programmable Gate Array(FPGA)-based General Hardware Accelerator(GHA) architecture.The GHA architecture implements the packet ...
FAN Hongwei,HU Yuxiang,LAN Julong
doaj   +1 more source

Photonic‐Enabled Energy‐Efficient Transparent Neuromorphic Computing Devices: A Review

Advanced Science, EarlyView.
Transparent photonic neuromorphic computing devices merge optics and brain‐inspired computing to overcome von Neumann bottlenecks with ultrafast, low‐energy processing. By exploiting transparent oxides, 2D materials, phase‐change materials, and hybrid heterostructures, these platforms enable photonic synapses, memory, and logic for see‐through edge ...
Shuvaraj Ghosh, Ki‐bum Lee, Junghyeon Lee, Seunghee Cho, Malkeshkumar Patel, Hangfei Li, Yu Wen, Ye Zhou, Joondong Kim   +8 more
wiley   +1 more source

Area efficient System-on-Programmable-Chip design for a wireless touch-triggered machining probe [PDF]

, 2011
In this paper, we present the design and implementation details of a System-on-Programmable-Chip (SoPC), which replaces the circuitry that controls the operation of a touch triggered machining probe with radio transmission capability.
Taskin Kocak, Kocak, T, Mimis, K, Konstantinos Mimis   +3 more
core   +1 more source

Design and FPGA-implementation of an improved adaptive fuzzy logic controller for DC motor speed control

Ain Shams Engineering Journal, 2014
This paper presents an improved adaptive fuzzy logic speed controller for a DC motor, based on field programmable gate array (FPGA) hardware implementation.
E.A. Ramadan, M. El-bardini, M.A. Fkirin
doaj   +1 more source

FPGA Implementation of A∗ Algorithm for Real-Time Path Planning

International Journal of Reconfigurable Computing, 2020
The traditional A∗ algorithm is time-consuming due to a large number of iteration operations to calculate the evaluation function and sort the OPEN list.
Yuzhi Zhou, Xi Jin, Tianqi Wang
doaj   +1 more source

Neuromorphic Devices and Computing for Sensing, Memory, and Control

Advanced Science, EarlyView.
This review introduces neuromorphic devices made from diverse materials. These devices mimic neuronal functions and architectures and, when integrated with artificial or biological computing, can form closed loops with neurons for pressure, optical, acoustic, and biochemical sensing and modulation.
Zhengguang Zhu, Nicholas Schaffer, Xiao Yang   +2 more
wiley   +1 more source

RG-ALU: A REVERSIBLE LOGIC GATE-BASED ARITHMETIC LOGIC UNIT IN AN FPGA [PDF]

Proceedings on Engineering Sciences
In this study, the method presents a novel for building a high-performance Arithmetic Logic Unit (ALU) by combining reversible logic gates with an HDL implementation on an FPGA. The objective of this strategy is to increase ALU efficiency by capitalizing
Kannan Ramakrishnan , Vidhya K Saveetha
doaj   +1 more source

Dataflow computation with intelligent memories emulated on field-programmable gate arrays (FPGAs) [PDF]

Microprocessors and Microsystems, 2002
Abstract This paper presents a new design that implements the data-driven (i.e. dataflow) computation paradigm with intelligent memories. Also, a relevant prototype that employs FPGAs is presented for the support of intelligent memory structures. Instead of giving the CPU the privileged right to decide what instructions to fetch in each cycle (as is ...
Segreen Ingersoll, Sotirios G. Ziavras
openaire   +1 more source

The Ubimus Plugging Framework: Deploying FPGA-Based Prototypes for Ubiquitous Music Hardware Design

Computers
The emergent field of embedded computing presents a challenging scenario for ubiquitous music (ubimus) design. Available tools demand specific technical knowledge—as exemplified in the techniques involved in programming integrated circuits of ...
Damián Keller, Aman Jagwani, Victor Lazzarini   +2 more
doaj   +1 more source