Multiband Real-Time Coherent Optical OFDM Reception up to 110 Gb/s with 600-km Transmission
IEEE Photonics Journal, 2010 We demonstrate field-programmable gate array (FPGA)-based multiband orthogonal frequency-division multiplexing (OFDM) signal reception after 600-km standard single-mode fiber (SSMF) transmission and 400-ps differential-group delay (DGD) at 110-Gb/s.
Simin Chen, Yiran Ma, William Shieh
doaj +1 more source
Self-Partial and Dynamic Reconfiguration Implementation for AES using FPGA [PDF]
, 2009 This paper addresses efficient hardware/software implementation approaches for the AES (Advanced Encryption Standard) algorithm and describes the design and performance testing algorithm for embedded system.
Alaoui Ismaili, Zine El Abidine +1 more
core +1 more source
Research on near-field focusing algorithm of reconfigurable reflect-array
The Journal of Engineering, 2019 In this study, the near-field beam focusing algorithm of reconfigurable reflect array for security imaging application is proposed. The proposed near-field focusing algorithm is based on classic array method, which is usually adopted for far-field ...
HongYan Liu +4 more
doaj +1 more source
Efficient Addition on Field Programmable Gate Arrays [PDF]
, 2001 We investigate average efficient adders for grid-based environments related to current Field Programmable Gate Arrays (FPGAs) and VLSI-circuits. Motivated by current trends in FPGA hardware design we introduce a new computational model, called the λ -wired grid model. The parameter λ describes the degree of connectivity of the underlying hardware. This
Jakoby, Andreas +1 more
openaire +2 more sources
Output data formatter for the Electronically Scanned Thinned Array Radiometer (ESTAR) instrument [PDF]
A prototype Output Data Formatter (ODF) for the ESTAR (Electronically Scanned Thinned Array Radiometer) instrument has been designed and tested. It employs programmable logic devices to format and tag correlator data for transmission to Earth.
Chren, William A., Jr.
core +1 more source
Implementasi Field Programmable Gate Array Dalam Perancangan Arithmetic-Logic Unit Dan Shifter [PDF]
, 2013 Paper ini membahas mengenai implementasi Field Programmable Gate Array (FPGA) untuk membuat Arithmetic-Logic Unit (ALU) merupakan core dari central processing unit (CPU). ALU terdiri dari dua fungsi, yaitu unit aritmetik dan unit logik.
Wibowo, F. W. (Ferry)
core
Advanced System-on-Chip Field-Programmable-Gate-Array-Powered Data Acquisition System for Pixel Detectors. [PDF]
Sensors (Basel), 2023 Jiménez-Sánchez J +5 more
europepmc +1 more source
Systems and methods for detecting a failure event in a field programmable gate array [PDF]
, 2009 An embodiment generally relates to a method of self-detecting an error in a field programmable gate array (FPGA). The method includes writing a signature value into a signature memory in the FPGA and determining a conclusion of a configuration refresh ...
Herath, Jeffrey A., Ng, Tak-Kwong
core +1 more source
IEEE AccessAdvanced memory optimization techniques are reviewed to enhance the performance of Convolutional Neural Networks (CNNs) and Spiking Neural Networks (SNNs) on hardware accelerators, addressing the real-world challenges in medical imaging.
N. Srikanth Prasad, S. Sundar
doaj +1 more source
A High-Performance and Cost-Effective Field Programmable Gate Array-Based Motor Drive Emulator. [PDF]
Micromachines (Basel), 2023 Hernandez J +2 more
europepmc +1 more source