Results 11 to 20 of about 21,529 (302)

Field Programmable Gate Array Applications—A Scientometric Review

Computation, 2019
Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems on chip or even artificial intelligence systems.
Juan Ruiz-Rosero, Gustavo Ramirez-Gonzalez, Rahul Khanna   +2 more
doaj   +1 more source

Space-time trellis codes: Field programmable gate array approach [PDF]

, 2020
In this paper, an effective method of implementation of Space-Time Trellis Codes (STTC) for 4-state on Field Programmable Gate Array is presented. To reach the very high data rates provided in STTC, a lot of expensive highspeed Digital Signal Processors (
Mallikarjuna Gowda C. P., Raju Hajare, C. P., Mallikarjuna Gowda, Hajare, Raju   +3 more
core   +1 more source

A Four-Context Programmable Optically Reconfigurable Gate Array With a Reflective Silver-Halide Holographic Memory

IEEE Photonics Journal, 2011
This paper presents a proposal for a four-context programmable optically reconfigurable gate array (PORGA) with a high-resolution reflective silver-halide holographic memory and a corresponding writer system.
Shinya Kubota, Minoru Watanabe
doaj   +1 more source

A Field Programmable Gate Array (FPGA) Based Non-Linear Filters for Gas Turbine Prognostics

International Journal of Prognostics and Health Management, 2021
The removal of noise from signals obtained through the health monitoring systems in gas turbines is an important consideration for accurate prognostics.
Jayant Kumar Nayak, Vatsala Prasad, Ranjan Ganguli   +2 more
doaj   +1 more source

Towards field-programmable photonic gate arrays [PDF]

Smart Photonic and Optoelectronic Integrated Circuits XXII, 2020
A version of this paper was presented at the OPTO conference in Photonics West ...
Daniel Pérez-López, A. López-Hernandez, A. Macho, P. Das Mahapatra, José Capmany   +4 more
openaire   +2 more sources

Implementing EW Receivers Based on Large Point Reconfigured FFT on FPGA Platforms [PDF]

International Journal of Computational Intelligence Systems, 2011
This paper presents design and implementation of digital receiver based on large point fast Fourier transform (FFT) suitable for electronic warfare (EW) applications.
He Chen, Xiujie Qu, Yuedong Luo, Chenwei Deng   +3 more
doaj   +1 more source

Parallelized Particle Swarm Optimization on FPGA for Realtime Ballistic Target Tracking

Sensors, 2023
This paper addresses the problem of tracking a high-speed ballistic target in real time. Particle swarm optimization (PSO) can be a solution to overcome the motion of the ballistic target and the nonlinearity of the measurement model. However, in general,
Juhyeon Park, Heoncheol Lee, Hyuck-Hoon Kwon, Yeji Hwang, Wonseok Choi   +4 more
doaj   +1 more source

Implementation of fractional order integrator/differentiator on field programmable gate array

Alexandria Engineering Journal, 2016
Concept of fractional order calculus is as old as the regular calculus. With the advent of high speed and cost effective computing power, now it is possible to model the real world control and signal processing problems using fractional order calculus ...
K.P.S. Rana, V. Kumar, N. Mittra, N. Pramanik   +3 more
doaj   +1 more source

Testing for the programming circuit of LUT-based FPGAs

, 1997
The programming circuit of look-up table based FPGAs consists of two shift registers, a control circuit and a configuration memory (SRAM) cell array. Because the configuration memory cell array can be easily tested by conventional test methods for RAMs ...
T. Inoue, Okamoto, Takuji, H. Michinishi, Yokohira, Tokumi, Inoue, Tomoo, T. Yokohira, T. Okamoto, Michinishi, Hiroyuki, Fujiwara, Hideo, H. Fujiwara   +9 more
core   +1 more source

Programmable Clock Distribution Using Switching Matrices for Field Programmable Gate Arrays

IEEE Access
Every digital systems using very large scale integration require clock distributions, for which a dedicated clock tree or a mesh clock is frequently used.
Ayumu Ogura, Minoru Watanabe, Nobuya Watanabe   +2 more
doaj   +1 more source