Results 31 to 40 of about 72,074 (292)

Evaluation of Single-Chip, Real-Time Tomographic Data Processing on FPGA - SoC Devices [PDF]

, 2018
A novel approach to tomographic data processing has been developed and evaluated using the Jagiellonian PET (J-PET) scanner as an example. We propose a system in which there is no need for powerful, local to the scanner processing facility, capable to ...
Białas, P., Curceanu, C., Czerwiński, E., Dulski, K., Flak, B., Gajos, A., Gorgol, M., Głowacz, B., Hiesmayr, B. C., Jasińska, B., Kacprzak, K., Kajetanowicz, M., Kisielewska, D., Korcyl, G., Kowalski, P., Kozik, T., Krawczyk, N., Krzemień, W., Kubicz, E., Mohammed, M., Moskal, P., Niedźwiecki, Sz., Pawlik-Niedźwiecka, M., Pałka, M., Raczyński, L., Rajda, P., Rudy, Z., Salabura, P., Sharma, N. G., Sharma, S., Shopa, R. Y., Silarski, M., Skurzok, M., Strzempek, P., Wieczorek, A., Wiślicki, W., Zaleski, R., Zgardzińska, B., Zieliński, M.   +38 more
core   +2 more sources

Implementation of fractional order integrator/differentiator on field programmable gate array

Alexandria Engineering Journal, 2016
Concept of fractional order calculus is as old as the regular calculus. With the advent of high speed and cost effective computing power, now it is possible to model the real world control and signal processing problems using fractional order calculus ...
K.P.S. Rana, V. Kumar, N. Mittra, N. Pramanik   +3 more
doaj   +1 more source

A binary self-organizing map and its FPGA implementation [PDF]

, 2009
A binary Self Organizing Map (SOM) has been designed and implemented on a Field Programmable Gate Array (FPGA) chip. A novel learning algorithm which takes binary inputs and maintains tri-state weights is presented.
Appiah, Kofi, Hobden, Mervyn, Hobden, Peter, Hunter, Andrew, Meng, Hongying, Pettit, Cy, Priestley, Nigel, Yue, Shigang   +7 more
core   +1 more source

Design of Novel Field Programmable Gate Array-Based Hearing Aid

IEEE Access, 2019
Hearing loss is one of the most common chronic diseases. For people with hearing loss, communicating with other people, particularly in an environment with considerable background noise, is difficult. Recently, several hearing aids have been developed to
Bor-Shing Lin, Po-Yu Yang, Ching-Feng Liu, Yi-Chia Huang, Chengyu Liu, Bor-Shyh Lin   +5 more
doaj   +1 more source

High-resolution FPGA-pulse width modulation applied to PFC 2 MHz converter using eGaN field effect transistor

The Journal of Engineering, 2019
This study proposes an implementation based on a low-cost field-programmable gate array (FPGA) of a high-resolution pulse width modulation applied on a single-phase power factor correction (PFC) converter operating with 2 MHz switch frequency.
José Augusto Arbugeri, Cesar Augusto Arbugeri, Samir Ahmad Mussa   +2 more
doaj   +1 more source

Programmable Clock Distribution Using Switching Matrices for Field Programmable Gate Arrays

IEEE Access
Every digital systems using very large scale integration require clock distributions, for which a dedicated clock tree or a mesh clock is frequently used.
Ayumu Ogura, Minoru Watanabe, Nobuya Watanabe   +2 more
doaj   +1 more source

Implementation of the block cipher Rijndael using Altera FPGA

Journal of Telecommunications and Information Technology, 2001
A short description of the block cipher Rijndael is presented. Hardware implementation by means of the FPGA (field programmable gate array) technology is evaluated. Im- plementation results compared with other hardware imple- mentations are summarized.
Piotr Mroczkowski
doaj   +1 more source

Implemetasi Komputasi Akar Kuadrat Resolusi Tinggi pada Field Programmable Gate Array (FPGA)

Jurnal Teknologi Informasi dan Ilmu Komputer, 2022
Komputasi akar kuadrat diperlukan pada beberapa proses pengendalian, diantaranya untuk Direct Torque Control (DTC) pada sistem penggerak motor yang membutuhkan proses perhitungan yang sangat cepat.
Muhammad Irfan, Hendra Setiawan
doaj   +1 more source

Scalability of spin FPGA: A Reconfigurable Architecture based on spin MOSFET

, 2011
Scalability of Field Programmable Gate Array (FPGA) using spin MOSFET (spin FPGA) with magnetocurrent (MC) ratio in the range of 100% to 1000% is discussed for the first time. Area and speed of million-gate spin FPGA are numerically benchmarked with CMOS
Gao Y., Hideyuki Sugiyama, Inokuchi T., Kazutaka Ikegami, Marukame T., Mizue Ishikawa, Nagamine Y., Sugiyama H., Takao Marukame, Tetsufumi Tanamoto, Tomoaki Inokuchi, Yoshiaki Saito   +11 more
core   +1 more source

Wykorzystanie struktur FPGA do implementacji algorytmów cyfrowego przetwarzania sygnałów [PDF]

Problemy Mechatroniki, 2017
W artykule opisano zaprojektowany, wykonany praktycznie oraz przebadany dwukanałowy tor cyfrowego przetwarzania sygnału z układem FPGA (Field-Programmable Gate Array), w którym zaimplementowano algorytmy DSP.
Stanisław GRZYWIŃSKI, Krzysztof ACHTENBERG   +1 more
doaj   +1 more source