Low-Resource Time-to-Digital Converters for Field Programmable Gate Arrays: A Review. [PDF]
Sensors (Basel)A fundamental aspect in the evolution of Time-to-Digital Converters (TDCs) implemented within Field-Programmable Gate Arrays (FPGAs), given the increasing demand for detection channels, is the optimization of resource utilization.
Real D, Calvo D.
europepmc +2 more sources
A self-timed multipurpose delay sensor for Field Programmable Gate Arrays (FPGAs). [PDF]
Sensors (Basel), 2013 This paper presents a novel self-timed multi-purpose sensor especially conceived for Field Programmable Gate Arrays (FPGAs). The aim of the sensor is to measure performance variations during the life-cycle of the device, such as process variability ...
Osuna CG, Ituero P, López-Vallejo M.
europepmc +2 more sources
Stage-Complete Mapping of Pairwise Monocular Structure-from-Motion to Field-Programmable Gate Arrays. [PDF]
J ImagingThis paper presents a stage-complete programmable-logic architecture for pairwise monocular structure from motion using calibrated, pre-undistorted 1920 × 1080 video.
Stamatakis P, Vourvoulakis J.
europepmc +2 more sources
Towards field-programmable photonic gate arrays [PDF]
Smart Photonic and Optoelectronic Integrated Circuits XXII, 2020 A version of this paper was presented at the OPTO conference in Photonics West ...
José Capmany +2 more
exaly +3 more sources
FlexKA: A Flexible Karatsuba Multiplier Hardware Architecture for Variable-Sized Large Integers
IEEE Access, 2023 The Karatsuba algorithm is an effective way to accelerate large integer multiplications through recursive function calls. However, existing hardware implementations of Karatsuba multipliers are limited to fixed operand sizes.
Byeongmin Kang, Hyungmin Cho
doaj +1 more source
FPGA-Based Controller for a Hybrid Grid-Connected PV/Wind/Battery Power System with AC Load
Energies, 2021 The development and optimization of a hybrid system composed of photovoltaic panels, wind turbines, converters, and batteries connected to the grid, is first presented.
Mohamed Yassine Allani +3 more
doaj +1 more source
Optical Multi-Context Blind Scrubbing for Field Programmable Gate Arrays
IEEE Photonics Journal, 2020 This paper presents aproposal of a new optical multi-context blind scrubbing that can not only increase the soft-error tolerance of the configuration memory of field programmable gate arrays (FPGAs) but also support high-speed dynamic reconfiguration ...
Yusuke Takaki, Minoru Watanabe
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Design and Implementation of Asynchronous Processor on FPGA
IEEE Access, 2022 Low-power and fault-tolerant features for microprocessors have been recognized as two of the greatest concerns in applications for edge devices. In this study, we propose asynchronous circuit design techniques for field-programmable gate arrays (FPGA ...
Ziho Shin, Myeong-Hoon Oh
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A detailed router for field-programmable gate arrays [PDF]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992 A detailed routing algorithm, called the coarse graph expander (CGE), that has been designed specifically for field-programmable gate arrays (FPGAs) is described. The algorithm approaches this problem in a general way, allowing it to be used over a wide range of different FPGA routing architectures. It addresses the issue of scarce routing resources by
Stephen Brown 0003 +2 more
openaire +3 more sources
Fast approximation of the top‐k items in data streams using FPGAs
IET Computers & Digital Techniques, 2023 Two methods are presented for finding the top‐k items in data streams using Field Programmable Gate Arrays (FPGAs). These methods deploy two variants of a novel accelerator architecture capable of extracting an approximate list of the topmost frequently ...
Ali Ebrahim, Jalal Khalifat
doaj +1 more source