Results 11 to 20 of about 10,771 (297)
Design and Implementation of Asynchronous Processor on FPGA
Low-power and fault-tolerant features for microprocessors have been recognized as two of the greatest concerns in applications for edge devices. In this study, we propose asynchronous circuit design techniques for field-programmable gate arrays (FPGA ...
Ziho Shin, Myeong-Hoon Oh
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Fast approximation of the top‐k items in data streams using FPGAs
Two methods are presented for finding the top‐k items in data streams using Field Programmable Gate Arrays (FPGAs). These methods deploy two variants of a novel accelerator architecture capable of extracting an approximate list of the topmost frequently ...
Ali Ebrahim, Jalal Khalifat
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Secure Configuration of Field Programmable Gate Arrays
Although SRAM programmed Field Programmable Gate Arrays (FPGA's) have come to dominate the industry due to their density and performance advantages over non-volatile technologies they have a serious weakness in that they are vulnerable to piracy and reverse engineering of the user design.
Tom Kean
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Interconnect Solutions for Virtualized Field-Programmable Gate Arrays
Contemporary datacenters are enhancing their compute capacity, power efficiency, and processing latency by integrating field-programmable gate arrays (FPGA).
Sadegh Yazdanshenas, Vaughn Betz
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Conducting functional control of field-programmable gate arrays
Approaches to accomplishing functional control of field-programmable gate arrays (FPGA) are described. The first part of the article describes the existing equipment that allows conducting functional tests of FPGAs.
A. A. Ogurtsov
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This paper presents a proposal for a four-context programmable optically reconfigurable gate array (PORGA) with a high-resolution reflective silver-halide holographic memory and a corresponding writer system.
Shinya Kubota, Minoru Watanabe
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Post-Measurement Adjustment of the Coincidence Window in Quantum Optics Experiments
We report on an electronic coincidence detection circuit for quantum photonic applications implemented on a field-programmable gate array (FPGA), which records each the time separation between detection events coming from single-photon detectors.
Jaime Carine +6 more
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Exploring FPGA Logic Block Architecture for Reduced Configuration Memory
The reduction of reconfiguration delay, during the partial dynamic reconfiguration of FPGAs, is important. In this context, the bitstream compression technique is one of the widely used techniques. These compression techniques only minimize the size of
HUSSAIN, F. +3 more
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Performance Analysis of Nanoelectromechanical Relay-Based Field-Programmable Gate Arrays
The energy consumption of field-programmable gate arrays (FPGA) is dominated by leakage currents and dynamic energy associated with programmable interconnect.
Tian Qin +4 more
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Modern computers’ network interface cards (NICs) are undergoing changes in order to handle greater data rates and assist with scaling problems caused by general-purpose CPU technology.
Sunkari Pradeep +4 more
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