Results 21 to 30 of about 10,771 (297)

Programmable Clock Distribution Using Switching Matrices for Field Programmable Gate Arrays

IEEE Access
Every digital systems using very large scale integration require clock distributions, for which a dedicated clock tree or a mesh clock is frequently used.
Ayumu Ogura, Minoru Watanabe, Nobuya Watanabe   +2 more
doaj   +1 more source

Intraveninio gliukozės tolerancijos testo metabolinės P sistemos įgyvendinimas apibendrintuoju kombinaciniu būdu / Intravenous glucose tolerance test metabolic P system implemented using unified combinative technique

Mokslas: Lietuvos Ateitis, 2019
Metabolic P (MP) systems are a part of the infobiotics research field. The intravenous glucose tolerance test (IVGTT) MP system models glucose-insulin interactions.
Darius Kulakovskis
doaj   +1 more source

Technology mapping of heterogeneous lookup table based field programmable gate arrays

, 1998
A lot of work has been done over the last decade on the logic synthesis and technology mapping of field programmable gate arrays (FPGAs) based on a single size of lookup table (LUT).
Inuani, Maurice Kilavuka, Inuani, Maurice Kilavuka.   +1 more
core   +1 more source

Field Programmable Gate Arrays (FPGAs) for Enhancing the Speed and Energy Efficiency of Quantum Dynamics Simulations

, 2020
We present the first application of field programmable gate arrays (FPGAs) as new, customizable hardware architectures that can be harnessed for the fast and energy-efficient calculation of quantum dynamics simulations of large chemical/material systems.
Jose, Rodriguez-Borbon, Amin, Kalantar, Wallid, Najar, Bryan, Wong, Sharma, Yamijala, M. Belen, Oviedo   +5 more
core   +1 more source

Testing for the programming circuit of LUT-based FPGAs

, 1997
The programming circuit of look-up table based FPGAs consists of two shift registers, a control circuit and a configuration memory (SRAM) cell array. Because the configuration memory cell array can be easily tested by conventional test methods for RAMs ...
T. Inoue, Okamoto, Takuji, H. Michinishi, Yokohira, Tokumi, Inoue, Tomoo, T. Yokohira, T. Okamoto, Michinishi, Hiroyuki, Fujiwara, Hideo, H. Fujiwara   +9 more
core   +1 more source

Field Programmable Gate Arrays (FPGAs) II [PDF]

, 2020
This Edited Volume Field Programmable Gate Arrays (FPGAs) II is a collection of reviewed and relevant research chapters, offering a comprehensive overview of recent developments in the field of Computer and Information Science.

core   +1 more source

A Tag Based Random Order Vector Reduction Circuit

IEEE Access, 2020
Vector reduction is a very common operation to reduce a vector into a single scalar value in many scientific and engineering application scenarios. Therefore a fast and efficient vector reduction circuit has great significance to the real-time system ...
Yihua Huang, Wenjin Huang, Rui Chen, Huangtao Wu, Ming Wei   +4 more
doaj   +1 more source

Digital Platform for Wafer-Level MEMS Testing and Characterization Using Electrical Response

Sensors, 2016
The uniqueness of microelectromechanical system (MEMS) devices, with their multiphysics characteristics, presents some limitations to the borrowed test methods from traditional integrated circuits (IC) manufacturing.
Nuno Brito, Carlos Ferreira, Filipe Alves, Jorge Cabral, João Gaspar, João Monteiro, Luís Rocha   +6 more
doaj   +1 more source

Integration of Low‐Voltage Nanoscale MoS2 Memristors on CMOS Microchips

Advanced Functional Materials, EarlyView.
This article presents the first monolithic integration of nanoscale MoS2‐based memristors into the back‐end‐of‐line of foundry‐fabricated CMOS microchips in a one‐transistor‐one‐resistor (1T1R) architecture. The MoS2‐based 1T1R cells exhibit forming‐free, nonvolatile resistive switching with ultra‐low operating voltages, low cycle‐to‐cycle variability ...
Jimin Lee, Sofía Cruces, Xiaohua Liu, Yang Chen, Vasilis A. Maroufidis, Janghyun Jo, Lukas Völkel, Dennis Braun, Michael Möller, Leon Brackmann, Holger Kalisch, Michael Heuken, Andrei Vescan, Rafal E. Dunin‐Borkowski, Joachim Mayer, Stefan Wiefels, Max C. Lemme   +16 more
wiley   +1 more source

FPGA-based dual-layer authentication scheme utilizing AES and ECC for unmanned aerial vehicles

EURASIP Journal on Wireless Communications and Networking
Unmanned aerial vehicles, commonly known as drones, face unique authentication challenges due to their distinct characteristics and operational environments.
Kumar Sekhar Roy, Murikipudi Sujith, Bandi Bhanu, Preethi, Ruhul Amin Hazarika   +4 more
doaj   +1 more source