Results 1 to 10 of about 1,042 (208)
Information Processing in Agriculture, 2014 Time to digital converter (TDC) is a key block for time-gated single photon avalanche diode (SPAD) arrays for Raman spectroscopy that applicable in the agricultural products and food analysis. In this paper a new dual slope time to digital converter that
Mahdi Rezvanyvardom +2 more
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High-Resolution Digital-to-Time Converter Implemented in an FPGA Chip
Applied Sciences, 2017 This paper presents the design and implementation of a new digital-to-time converter (DTC). The obtained resolution is 1.02 ps, and the dynamic range is about 590 ns. The experimental results indicate that the measured differential nonlinearity (DNL) and
Hai Wang, Min Zhang, Yan Liu
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Mokslas: Lietuvos Ateitis, 2017 Time to digital converter (TDC) is one of the main blocks of all-digital frequency synthesizer (FS), where it is used as phase detector. The output of TDC is digital, therefore it introduces quantization noise to the output of FS.
Marijan Jurgo, Romualdas Navickas
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Applied Sciences, 2022 This paper presents a 19 ps precision and 170 M samples/s time-to-digital converter (TDC) in FPGA. Through the direct count method and tapped delay line method, the coarse count and fine count can be extracted, respectively.
Mengdi Zhang +3 more
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Sensors, 2019 The paper is focused on design of time-to-digital converters based on successive approximation (SA-TDCs—Successive Approximation TDCs) using binary-scaled delay lines in the feedforward architecture. The aim of the paper is to provide a tutorial on
Jakub Szyduczyński +2 more
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Linearity improvement of UltraScale+ FPGA-based time-to-digital converter
Nuclear Engineering and Technology, 2023 Time-to-digital converters (TDCs) based on the tapped delay line (TDL) architecture have been widely used in various applications requiring a precise time measurement.
Jaewon Kim +4 more
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Calibration Methods for Time-to-Digital Converters
Sensors, 2023 In this paper, two of the most common calibration methods of synchronous TDCs, which are the bin-by-bin calibration and the average-bin-width calibration, are first presented and compared. Then, an innovative new robust calibration method for asynchronous TDCs is proposed and evaluated. Simulation results showed that: (i) For a synchronous TDC, the bin-
Khaddour, Wassim +4 more
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Analysis and Design of a New Voltage Amplifier Applying In The Time and Voltage Domain Converters [PDF]
مجله مدل سازی در مهندسی, 2016 In this paper a new voltage amplifier is investigated which is employed in the time and voltage domain converters such as analog to digital converters (ADCs) and time to digital converters (TDCs).
نازنین معلمیان +2 more
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Technology Independent ASIC Based Time to Digital Converter
IEEE Access, 2020 This paper proposes a design methodology for a synthesizable, fully digital TDC architecture. The TDC was implemented using a hardware description language (HDL), which improves portability between platforms and technologies and significantly reduces ...
Rui Machado +3 more
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A Digital PLL with a Stochastic Time-to-Digital Converter [PDF]
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers., 2006 A new dual-loop digital phase-locked loop (DPLL) architecture is presented. It employs a stochastic time-to-digital converter (STDC) and a high-frequency delta-sigma dithering to achieve wide PLL bandwidth and low jitter at the same time. The STDC exploits the stochastic properties of a set of latches to achieve high resolution.
Volodymyr Kratyuk +4 more
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