A High Resolution Vernier Digital-to-Time Converter Implemented with 65 nm FPGA
Applied Sciences, 2019 In this paper, a digital-to-time converter (DTC) based on the three delay lines (3D) Vernier principle is proposed and implemented with field programmable gate arrays (FPGAs).
Chenggang Yan, Chen Hu, Jianhui Wu
doaj +4 more sources
High-Linearity High-Resolution Time-of-Flight Linear-Array Digital Image Sensor Using Time-Domain Feedback [PDF]
Sensors, 2021 This paper presents a high-linearity high-resolution time-of-flight (ToF) linear-array digital image sensor using a time-domain negative feedback technique.
Juyeong Kim +3 more
doaj +2 more sources
An 8‐bit digital‐to‐time converter with pre‐skewing and time interpolation
IET Circuits, Devices and Systems, 2021 This study presents an 8‐bit delay line digital‐to‐time converter (DTC) with pre‐skewing and digital time interpolation. Pre‐skewing that lowers the per‐stage‐delay of delay lines beyond that set by the chosen technology is investigated.
Daniel Junehee Lee +3 more
doaj +2 more sources
A Reference-Sampling Based Calibration-Free Fractional-N PLL with a PI-Linked Sampling Clock Generator [PDF]
Sensors, 2021 Sampling-based PLLs have become a new research trend due to the possibility of removing the frequency divider (FDIV) from the feedback path, where the FDIV increases the contribution of in-band noise by the factor of dividing ratio square (N2).
Jae-Soub Han +7 more
doaj +2 more sources
High-Resolution Digital-to-Time Converter Implemented in an FPGA Chip
Applied Sciences, 2017 This paper presents the design and implementation of a new digital-to-time converter (DTC). The obtained resolution is 1.02 ps, and the dynamic range is about 590 ns. The experimental results indicate that the measured differential nonlinearity (DNL) and
Hai Wang, Min Zhang, Yan Liu
doaj +2 more sources
Digital-to-Time Converter with 3.93 ps Resolution Implemented on FPGA Chips
IEEE Access, 2017 In this paper, a digital-to-time converter (DTC) based on the principle of quantified phase shift resolution (QPSR) is proposed and tested. The QPSR principle is realized by analyzing the phase relationship between two periodic signals, which ...
Min Zhang, Hai Wang, Yan Liu
doaj +3 more sources
Linearized 9-Bit Hybrid LBDD PWM Modulator for Digital Class-BD Amplifier [PDF]
International Journal of Electronics and Telecommunications, 2021 The paper presents an original architecture and implementation of 9-bit Linearized Pulse Width Modulator (LPWM) for Class-BD amplifier, based on the hybrid method using STM32 microcontroller and Programmable Tapped Delay Line (PTDL).
Wojciech Kołodziejski +1 more
doaj +1 more source
A 0.002‐mm2 8‐bit 1‐MS/s low‐power time‐based DAC (T‐DAC)
IET Circuits, Devices and Systems, 2021 Digital‐to‐analogue converters (DACs) are essential blocks for interfacing the digital environment with the real world. A novel architecture, using a digital‐to‐time converter (DTC) and a time‐to‐voltage converter (TVC), is employed to form a low‐power ...
Ali H. Hassan +4 more
doaj +1 more source
IEEE Open Journal of Circuits and Systems, 2023 The increasing demand for high performance and energy efficiency in Artificial Neural Networks (ANNs) accelerators has driven a wide range of application-specific integrated circuits (ASICs).
Hamza Al Maharmeh +3 more
doaj +1 more source
A Low Power All-Digital PLL With −40dBc In-Band Fractional Spur Suppression for NB-IoT Applications
IEEE Access, 2019 This paper proposes a low-power fractional-N all-digital PLL (ADPLL) for the narrow-band Internet-of-Things applications. Multi-step lock controlling and oscillator tuning word coarse prediction algorithms help to accelerate the locking process to less ...
Na Yan +6 more
doaj +1 more source