Results 41 to 50 of about 474 (139)

PLA2G16‐Mediated Tetracosatetraenoic Acid Rewires Fatty Acid Oxidation to Impair CD8+ T Cell Immune Function in Promoting Breast Cancer Lung Metastasis

Advanced Science, Volume 13, Issue 6, 30 January 2026.
Illustrating how tumor‐derived PLA2G16 regulates tetracosatetraenoic acid (C24:4 (n‐6)) accumulation and CD8+ T cell activation via the C24:4‐PPARα‐FAO axis in early metastatic niches, thereby promoting lung metastasis of triple‐negative breast cancer.
Yubi Gan, Die Meng, Lei Lang, Jing Luo, Peijin Dai, Chao Chang, Zexiu Lu, Yuetong Guo, Rui Wang, Shanchun Chen, Xi Tang, Yixuan Hou, Dongmei Tan, Manran Liu   +13 more
wiley   +1 more source

A Time Amplifier Assisted FDC and DTC Linearization for Digital Fractional-N PLLs [PDF]

, 2022
OF THE DISSERTATION A Time Amplifier Assisted FDC and DTC Linearization for Digital Fractional-N PLLs by Eslam Mohamed Sayed Ali Helal Doctor of Philosophy in Electrical Engineering (Electronic Circuits and Systems) University of California San Diego,
Helal, Eslam Mohamed Sayed Ali
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Advancements in Targeted Radiopharmaceuticals: Innovations in Diagnosis and Therapy for Enhanced Cancer Management

ChemBioChem, Volume 27, Issue 1, January 2026.
Radiopharmaceuticals enable precise cancer diagnosis and targeted therapy by combining radioactive isotopes with carrier molecules. This review summarizes advances from 2014 to 2025, emphasizing probe design, click chemistry, novel targets, and nanodelivery systems.
Mohd Sayeed Shaikh, Rupesh R. Kurhade, Abrar A. M. Siddiqui, Shaikh Shahbaz A. Majeed, Thomas J. Webster, Mohammad Intakhab Alam, Abdul Wasy Zia, Md. Faiyazuddin   +7 more
wiley   +1 more source

A Timing Skew Correction Technique in Time-Interleaved ADCs Based on a DeltaSigma Digital-to-Time Converter

, 2021
This paper reviews state-of-the-art skew correction methods in time-interleaved (TI) analog-to-digital converters (ADCs) and introduces a novel mixed-signal skew correction technique based on dithering the control word of a digital-totime converter (DTC),
G. Be', L. Bertulessi, M. Mercandelli
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Performance Improvement of PMSG‐Based Wind Energy Systems via Sensorless FS‐Predictive Current Control With MRAS and MPPT‐OTC Integration

IET Electric Power Applications, Volume 20, Issue 1, January/December 2026.
This paper proposes a hybrid sensorless control strategy for a permanent magnet synchronous generator (PMSG)‐based wind energy conversion system (WECS). The approach integrates finite‐set predictive current control (FS‐PCC), a model reference adaptive system (MRAS) estimator and an optimal torque control maximum power point tracking (MPPT‐OTC) method ...
Hicham Sayhi, Amor Bourek, Abdelkarim Ammar, Ali Teta, Ahmed Chennana, Abdelaziz Rabehi, Mohamed Benghanem, Takele Ferede Agajie   +7 more
wiley   +1 more source

All-digital pulse-expansion-based CMOS digital-to-time converter

, 2017
[[abstract]]This paper presents a new all-digital CMOS digital-to-time converter (DTC) based on pulse expansion. Pulse expansion is achieved using an all-digital pulse-mixing scheme that can effectively improve the timing resolution and enable the DTC to
CC, Chen;CH, Chu
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Multi-channel high-resolution digital-to-time pattern generator IP-core for FPGAs and SoCs

, 2021
LAUREA MAGISTRALELa richiesta di forme d'onda accurate e precise, caratterizzate da una risoluzione nell'ordine dei picosecondi e da un elevato Full-Scale Range, è aumentata notevolmente nel corso degli ultimi decenni, insieme ai campi d'applicazione di
FERRARESI, FEDERICO
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Recent Advances in Hybrid, Plug‐In, Battery, and Fuel Cell EVs: Control Schemes, Modes, Converter Topologies, and Pros and Cons

IET Electrical Systems in Transportation, Volume 2026, Issue 1, 2026.
Direct current (DC)–DC converters are the backbone of electric vehicle (EV) power trains, enabling efficient and bidirectional energy flow between the battery, high‐voltage (HV) DC link, and auxiliary rails under tight isolation, gain, ripple, and electromagnetic interference (EMI) constraints.
Abhilash Sakhare, Suresh Mikkili, Praveen Kumar Bonthagorla, Fabio Crescimbini   +3 more
wiley   +1 more source

A Dual-Alternating-Slope Digital-to-Time Converter Leveraging Mismatch to Improve Delay Step Size [PDF]

This article introduces a dual-alternating-slope digital-to-time converter (DASDTC) topology that reduces the dependency of DTC delay on component values and power supply.
Jain, Nimit, van Rumpt, Harm, Nauta, Bram, Klumperink, Eric A.M.   +3 more
core   +1 more source

A 31-μ W, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS

, 2019
This article proposes a power-efficient highly linear capacitor-array-based digital-to-time converter (DTC) using a charge redistribution constant-slope approach.
Siriburanon, Teerachot (author), Siriburanon, Teerachot, Zong, Z. (author), Zong, Zhirui, Zhang, Feifei (author), Hu, Suoping, Chen, Peng, Zhang, Feifei, Staszewski, Robert Bogdan, Hu, Suoping (author), Staszewski, R.B. (author), Chen, Peng (author)   +11 more
core   +1 more source