Digital-to-time converter dtc - Open Access .click

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Entwicklung von analytischen Verhaltensmodellen für Digitally Controlled Edge Interpolator (DCEI) basierte Digital-to-Time Converter (DTC) Schaltungen

, 2019
Digital-to-time converter (DTC) circuits enable various applications in the area of frequency synthesis. Phase interpolator (PI) circuits are popular DTC fine tuning elements, however, their high nonlinearity is a major drawback.
Sievert, Sebastian
core

Stato dell'arte dei sistemi digital to time converter (DTC)

, 2019
LAUREA MAGISTRALEIl testo descrive l’analisi della tecnologia dei sistemi DTC implementati digitalmente. La risoluzione dei DTC implementati su FPGA raggiungono gli ordini del picosecondo e l'intervallo dinamico è di qualche centinaia di nanosecondi ...
GALBURA, ECATERINA
core

4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology

, 2023
The quest of increasingly higher mobile uplink/downlink data-rates has recently driven the communication industry to set extremely challenging requirements on the integrated jitter of local oscillators [1]. In fractional-N PLLs, the adoption of a digital-
Castoro, Giacomo +9 more
core +1 more source

Dynamic bias and jitter reduction in a highly linear Digital-to-Time Converter for digital PLLs in 28nm CMOS technology

, 2023
LAUREA MAGISTRALEL'obiettivo della tesi è di migliorare le performance di rumore di un'esistente architettura di Digital-to-Time Converter (DTC) ad alta linearità, con lo scopo di rendere realizzabili PLL digitali ad alta purezza spettrale e basso ...
Salvi, Pietro
core

Digital-to-Time Converter for pulse train generation based on Look-Up Tables in FPGA

, 2018
A Digital-to-Time Converter (DTC) is presented which allows to generate pulse train with resolution of 250 ps within 32 ns operation range. The converter is implemented in off-the-shelf Spartan-6 Field-Programmable Gate Array (FPGA) device, manufactured ...
Szplet, R., Różyc, K., Kwiatkowski, P.
core

A 79.3fsrms Jitter Fractional-N Digital PLL Based on a DTC Chopping Technique

This work presents a fractional- N digital PLL leveraging a digital-to-time converter (DTC) chopping technique to improve spectral purity and jitter.
Castoro, Giacomo +8 more
core +1 more source

Analysis of Effect of Digital/ TIME Converter Resolution When Being Used in Fractional-N Digital Bang-Bang Phase-locked-loops

, 2022
In this paper, based on an analysis of operating principle of digital/time converter (DTC) employed in fractional-N digital Bang-Bang phase-locked-loops, the authors derive an estimation of frequency of fractional spur appearing in the phase noise power ...
Minh, V. T. (Võ) +3 more
core

High-Precision Digital-to-Time Converter with High Dynamic Range for 28 nm 7-Series Xilinx FPGA and SoC Devices [PDF]

Over the last ten years, the need for high-resolution time-domain digital signal production has grown exponentially. More than ever, applications call for a digital-to-time converter (DTC) that is extremely accurate and precise.
Ronconi, Enrico +17 more
core +1 more source

Non-linearity cancellation technique in a variable slope digital-to-time converter for digital PLLs in 28nm CMOS technology

, 2023
LAUREA MAGISTRALECon l'aumento esponenziale della richiesta di velocità elevate per la trasmissione dei dati, i moderni protocolli di comunicazione wireless richiedono trasmettitori sempre più veloci, caratterizzati da un'elevata purezza spettrale ...
Dell'Orto, Riccardo
core

A Low-Jitter Fractional-$N$ Digital PLL Adopting a Reverse-Concavity Variable-Slope DTC [PDF]

This article presents a fractional-N digital-to-time converter (DTC)-based digital phase-locked loop (PLL), achieving simultaneously low phase noise and low spurious tones.
Castoro, Giacomo +6 more
core +1 more source

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