Results 71 to 80 of about 118,703,232 (151)

A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC

open access: yes
Modern fractional-N PLLs used as low-jitter local oscillators for wireless systems generally adopt a digital-to-time converter (DTC) to cancel-out the quantization-error (QE) induced by dithering the modulus control of the frequency divider in feedback ...
Castoro, Giacomo   +6 more
core   +1 more source

All-Digital Phase-Locked Loop Design for Phase Noise Improvement Using Model Predictive Controller and TDC-DTC at S-Band

open access: yes
This paper presents the design of a fully digital phase-locked loop (ADPLL) aimed at improving phase noise performance in frequency synthesizers. The proposed system integrates a digital frequency-phase detector using a Time-to-Digital Converter (TDC ...
S. Mohammad Hassan Javadzadeh   +1 more
core   +1 more source

Model Predictive Direct Torque Control and Fuzzy Logic Energy Management for Multi Power Source Electric Vehicles. [PDF]

open access: yesSensors (Basel), 2022
Kakouche K   +9 more
europepmc   +1 more source

Rapid scan EPR: Automated digital resonator control for low-latency data acquisition. [PDF]

open access: yesJ Magn Reson, 2022
O'Connell RC   +4 more
europepmc   +1 more source

A Low Jitter and Low Spur Fractional-N Digital PLL Based on a DTC Chopping Technique

open access: yes
This work presents a digital-to-time converter (DTC)-based fractional-N digital phase-locked loop (PLL) designed to achieve simultaneously low jitter and low spurs.
Castoro, Giacomo   +8 more
core   +1 more source

A Programmable Time Measurement Architecture for Embedded Memory Characterization

open access: yes, 2005
This paper describes a programmable time measurement architecture that facilitates memory characterization. We have created a novel standalone time measurement architecture that can measure rise time, fall time, pulse width and propagation delay time ...
Ross, Neil   +2 more
core   +1 more source

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