Results 61 to 70 of about 118,703,232 (151)
Molecular Oncology, Volume 20, Issue S1, Page 1-692, August 2026.Abstracts submitted to the ‘EACR 2026 Congress: Innovative Cancer Science’, from 08–11 June 2026 and accepted by the Congress Organising Committee are published in this Supplement of Molecular Oncology, an affiliated journal of the European Association for Cancer Research (EACR).
wiley +1 more source
, 2017 Apparatus and methods for a digital-to-time converter (DTC) are provided. In an example, a DTC can include a phase interpolator and a ring oscillator.
Passamani Antonio +2 more
core
, 2022 MasterThis work presents a low-noise millimeter-wave fractional-N digital phase-locked-loop (PLL) architecture with a digital-intensive nonlinearity calibration.
정기창
core
A Low-Jitter Fractional-$N$ Digital PLL Adopting a Reverse-Concavity Variable-Slope DTC [PDF]
This article presents a fractional-N digital-to-time converter (DTC)-based digital phase-locked loop (PLL), achieving simultaneously low phase noise and low spurious tones.
Castoro, Giacomo +6 more
core +1 more source
, 2023 65 p.This thesis explores the application of hardware-in-the-loop (HIL) simulation to enhance the control of Permanent Magnet Synchronous Machines (PMSMs) by integrating a bidirectional AC/DC converter with a Direct Torque Control-Space Vector ...
Bendada, Abderrahmane +2 more
core
A 58.9fs-Jitter Fractional-N Digital PLL Using a Double-Edge Variable-Slope DTC
This work presents a fractional-N digital PLL achieving low-jitter by leveraging the combination of a XOR frequencydoubler and a power-efficient double-edge variable-slope digital-to-time converter (DTC).
M. Rossoni +11 more
core +1 more source
A Dual-Alternating-Slope Digital-to-Time Converter Leveraging Mismatch to Improve Delay Step Size [PDF]
This article introduces a dual-alternating-slope digital-to-time converter (DASDTC) topology that reduces the dependency of DTC delay on component values and power supply.
Jain, Nimit +3 more
core +1 more source
, 2021 This paper describes a 10-bit digital-to-time converter (DTC) utilizing the glitch-free dual reset method and switchable supply regulation scheme for high linearity regardless of supply ripple noise and input signal speed.
Inho Jung
core
A Low-Noise Fractional-$N$ Digital PLL Using a Resistor-Based Inverse-Constant-Slope DTC
This work presents a digital-to-time converter (DTC)-based fractional- N phase-locked loop (PLL) achieving low jitter and low spurs. Thanks to the proposed resistor-based inverse-constant-slope (R-ICS) DTC, the DTC random jitter is drastically reduced ...
Castoro, Giacomo +6 more
core +1 more source
A Low-Jitter Fractional-N Digital PLL With Spur Cancellation Based on a Multi-DTC Topology
This work presents a low-jitter and low-spur fractional-N digital phase-locked loop (PLL) with a multi-path topology, each path having its own digital-to-time converter (DTC) and phase detector (PD).
Castoro, Giacomo +8 more
core +1 more source