Results 61 to 70 of about 474 (139)

Study on the Integration Strategy of Online EOL Testing of Pure Electric Vehicle Power Battery. [PDF]

Sensors (Basel), 2023
Wang H, Qin H.
europepmc   +1 more source

A 3.5-6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise

, 2016
We present a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth all-digital PLL (ADPLL). It employs a MASH ΔΣ time-to-digital converter (TDC) to achieve low in-band phase noise, and a wide-tuning range digitally-controlled oscillator ...
Ying Wu, Shahmohammadi, Mina, Robert Bogdan Staszewski, Wu, Ying, Staszewski, Robert Bogdan, Yue Chen, Ping Lu, Chen, Yue, Lu, Ping, Mina Shahmohammadi   +9 more
core   +1 more source

Model Predictive Direct Torque Control and Fuzzy Logic Energy Management for Multi Power Source Electric Vehicles. [PDF]

Sensors (Basel), 2022
Kakouche K, Rekioua T, Mezani S, Oubelaid A, Rekioua D, Blazek V, Prokop L, Misak S, Bajaj M, Ghoneim SSM.   +9 more
europepmc   +1 more source

Injection locked ring oscillator based digital-to-time converter and method for providing a filtered interpolated phase signal

, 2017
Apparatus and methods for a digital-to-time converter (DTC) are provided. In an example, a DTC can include a phase interpolator and a ring oscillator.
Passamani Antonio, Ponton Davide, Bevilacqua Andrea   +2 more
core  

Rapid scan EPR: Automated digital resonator control for low-latency data acquisition. [PDF]

J Magn Reson, 2022
O'Connell RC, Tseytlin O, Bobko AA, Eubank TD, Tseytlin M.   +4 more
europepmc   +1 more source

Extended Kalman Filter design for sensorless sliding mode predictive control of induction motors without weighting factor: An experimental investigation. [PDF]

PLoS One, 2023
Chebaani M, Mahmoud MM, Tazay AF, Mosaad MI, Nouraldin NA.   +4 more
europepmc   +1 more source

A Low-Jitter Fractional-N Digital PLL With Spur Cancellation Based on a Multi-DTC Topology

This work presents a low-jitter and low-spur fractional-N digital phase-locked loop (PLL) with a multi-path topology, each path having its own digital-to-time converter (DTC) and phase detector (PD).
Castoro, Giacomo, Rossoni, Michele, Tesolin, Francesco, Buccoleri, Francesco, Lacaita, Andrea L., Dartizio, Simone M., Cherniak, Dmytro, Samori, Carlo, Levantino, Salvatore   +8 more
core   +1 more source

Designing of an Enhanced Fuzzy Logic Controller of an Interior Permanent Magnet Synchronous Generator under Variable Wind Speed. [PDF]

Sensors (Basel), 2023
Masoud UMM, Tiwari P, Gupta N.
europepmc   +1 more source

A high-resolution DLL-based digital-to-time converter for DDS applications

, 2002
A Digital-to-Time Converter (DTC) based on a Delay-Locked Loop (DLL) for phase interpolation in Direct Digital Synthesis (DDS) applications is described. The conversion is made in two steps using digitally controllable delay cells with configurable shunt-
FANUCCI, LUCA, BARONTI, FEDERICO, RONCELLA, ROBERTO, SALETTI, ROBERTO, D. LUNARDINI   +4 more
core  

A 58.9fs-Jitter Fractional-N Digital PLL Using a Double-Edge Variable-Slope DTC

This work presents a fractional-N digital PLL achieving low-jitter by leveraging the combination of a XOR frequencydoubler and a power-efficient double-edge variable-slope digital-to-time converter (DTC).
M. Rossoni, G. Castoro, D. Lodi Rizzini, F. Tesolin, P. Salvi, S. Gallucci, S. M. Dartizio, R. Moleri, S. Levantino, D. Fagotti, G. R. Trotta, A. L. Lacaita   +11 more
core   +1 more source