A High-Linearity Digital-to-Time Converter Technique: Constant-Slope Charging [PDF]
IEEE Journal of Solid-State Circuits, 2015 A digital-to-time converter (DTC) controls time delay by a digital code, which is useful, for example, in a sampling oscilloscope, fractional-N PLL, or time-interleaved ADC.
Bram Nauta +2 more
exaly +3 more sources
A Sensitive Method to Measure the Integral Nonlinearity of a Digital-to-Time Converter Based on Phase Modulation [PDF]
IEEE Transactions on Circuits and Systems II: Express Briefs, 2015 A digital-to-time converter (DTC) produces a time delay based on a digital code. Similar to data converters, linearity is a key metric for a DTC and it can be characterized by its integral nonlinearity (INL). However, measuring the INL of a subpicosecond-
Bram Nauta +2 more
exaly +2 more sources
A Digital to Time Converter With Fully Digital Calibration Scheme for Ultra-Low Power ADPLL in 40 nm CMOS [PDF]
, 2015 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, 24 - 27 May 2015In this paper, a digital-to-time converter (DTC) assisting a time-to-digital converter (TDC) as a fractional phase error detector in an ultra-low power ...
Robert Bogdan Staszewski +2 more
exaly +2 more sources
An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs [PDF]
IEEE Journal of Solid-State Circuits, 2014 Digital fractional-N phase-locked loops (PLLs) are an attractive alternative to analog PLLs in the design of frequency synthesizers for wireless applications.
Carlo Samori +2 more
exaly +2 more sources
An 8-bit digital-to-time converter with pre-skewing and time interpolation
, 2022 This study presents an 8‐bit delay line digital‐to‐time converter (DTC) with pre‐skewing and digital time interpolation. Pre‐skewing that lowers the per‐stage‐delay of delay lines beyond that set by the chosen technology is investigated.
Daniel Junehee Lee (10854495) +3 more
core +1 more source
Exponential extended flash time-to-digital converter [PDF]
, 2016 IEEE International Nordic-Mediterranean Workshop on Time-to-Digital Converters and Applications (NoMe - TDC 2016), Krakow, Poland, June, 2016The digital-to-time converter (DTC)-based all- digital phase locked loop (ADPLL) attracts more and more attention
Chen, Peng +3 more
core +1 more source
Improved FPGA time-to-digital converter architecture to improve precision, converter linearity and reduce dead-time [PDF]
, 2020 Time-to-digital converters (TDCs) and time correlated single photon counters (TCSPC) are instruments commonly used in LiDAR systems, quantum optics experiments and many other applications.
Richard W. Nock +5 more
core +1 more source
A Calibration-Free Digital-to-Time Converter for Phase Interpolation-Based Fractional-N PLLs
, 2023 In this paper, a fractional frequency division phase-locked loop based on phase interpolation is proposed and implemented using the TSMC 0.11 μm CMOS process.
Weishuang Liang, Yebing Gan, Qi Liu
core +1 more source
A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS [PDF]
, 2017 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), Grand Hilton Hotel, Seoul, Korea, 6-8 November 2017This paper proposes a power-efficient capacitor-array-based digital-to-time converter (DTC) using a constant-slope approach.
Siriburanon, Teerachot +12 more
core +2 more sources
IEEE AccessThis paper presents a DTC-based snapshot all-digital phase-locked loop (ADPLL) that achieves robust fractional spur suppression and low phase noise with compact circuit implementation.
Kihoon Kwon +13 more
doaj +1 more source